Semiconductor device having metal gate and method for manufacturing semiconductor device having metal gate

1. A method for manufacturing a semiconductor device having metal gate, comprising:

providing a substrate comprising at least a transistor and an interlayer dielectric (ILD) layer surrounding the transistor formed thereon, the transistor comprising a dummy gate;

performing a first removal process to remove a portion of the dummy gate to form a first recess in the transistor;

performing an etching process to remove a portion of the ILD layer to widen the first recess and to form a widened first recess;

performing a second removal process to remove the dummy gate entirely to form a second recess in the transistor after the etching process;

forming a metal gate in the second recess; and

forming an insulating cap layer on the metal gate.

2. The method for manufacturing the semiconductor device having metal gate according to claim 1 , wherein the transistor comprises a pair of spacers formed on sidewall of the dummy gate.

3. The method for manufacturing the semiconductor device having metal gate according to claim 2 , wherein the etching process is performed to remove a portion of the spacers.

4. The method for manufacturing the semiconductor device having metal gate according to claim 2 , further comprising a contact etch stop layer (CESL) formed on the substrate, and the CESL covering the spacer.

5. The method for manufacturing the semiconductor device having metal gate according to claim 4 , wherein the etching process is performed to remove a portion of the CESL.

6. The method for manufacturing the semiconductor device having metal gate according to claim 1 , wherein the portion of the ILD layer removed by the etching process comprises a width, and the width is between 3 nanometers (nm) and 8 nm.

7. The method for manufacturing the semiconductor device having metal gate according to claim 1 , wherein the metal gate comprises at least a work function metal layer, a filling metal layer and a high-k gate dielectric layer.

8. The method for manufacturing the semiconductor device having metal gate according to claim 7 , further comprising:

sequentially forming the high-k gate dielectric layer, the work function metal layer and the filling metal layer in the widened first recess and the second recess;

performing a planarization process to remove a portion of the high-k gate dielectric layer, a portion of the work function metal layer and a portion of the filling metal layer to form the metal gate; and

performing a metal etching process to remove a portion of the metal gate from the widened first recess.

9. The method for manufacturing the semiconductor device having metal gate according to claim 8 , wherein a top surface of the metal gate and a bottom surface of the widened first recess are coplanar after the metal etching process.

10. The method for manufacturing the semiconductor device having metal gate according to claim 8 , wherein a top surface of the metal gate is lower than a bottom surface of the widened first recess after the metal etching process.

11. The method for manufacturing the semiconductor device having metal gate according to claim 8 , wherein a top surface of the metal gate is higher than a bottom surface of the widened first recess after the metal etching process.

12. The method for manufacturing the semiconductor device having metal gate according to claim 1 , wherein a top surface of the insulating cap layer and a top surface of the ILD layer are coplanar.

13. The method for manufacturing the semiconductor device having metal gate according to claim 1 , further comprising forming a contact plug in the ILD layer.