Adaptive digital delay line for characterization of clock uncertainties
An integrated circuit (IC) measures uncertainties in a first signal. The IC comprises a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal. The IC further comprises a digital delay line (DDL) comprising a first delay chain of delay elements having input to receive the first delayed signal. The DDL further comprises a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading. The DDL additionally comprises a decoder to generate a digital signature from the digital reading and a controller to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
1. An integrated circuit (IC) for measuring uncertainties in a first signal, the IC comprising:
a programmable delay circuit to introduce a programmable delay to the first signal to generate a first delayed signal; and
a digital delay line (DDL) comprising:
a first delay chain of delay elements having input to receive the first delayed signal; and
a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading; and
a controller to adjust the programmable delay of the programmable delay circuit based on a combination of the corresponding bits of the digital reading.
2. The IC of claim 1 , wherein the first signal is a clock signal.
3. The IC of claim 1 , wherein the set of storage elements comprises a set of flip-flops, each flip flop comprising a clock input to receive a clock signal.
4. The IC of claim 1 , wherein the programmable delay circuit comprises:
a series of fixed delay stages having an input to receive the first signal; and
a multiplexer comprising:
a plurality of inputs, each input coupled to an output of a corresponding fixed delay stage of the series of fixed delay stages;
an output to provide the first delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a control signal from the controller.
5. The IC of claim 1 , wherein the programmable delay circuit comprises:
a series of fixed delay stages having an input to receive the first signal;
a first multiplexer comprising:
a plurality of inputs, each input coupled to an output of a corresponding fixed delay stage of the series of fixed delay stages;
an output to provide an intermediate delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a first control signal from the controller;
a second delay chain of delay elements having an input coupled to the output of the first multiplexer; and
a second multiplexer comprising:
a plurality of inputs including an input coupled to the output of the first multiplexer and inputs coupled to outputs of corresponding delay elements of the second delay chain;
an output to provide the first delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a second control signal from the controller.
6. The IC of claim 1 , further comprising:
a decoder to generate a digital signature from the digital reading.
7. The IC of claim 6 , wherein the controller is to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
8. The IC of claim 7 , further comprising:
a characterization circuit to characterize a parameter of the first signal based on the programmed delay that resulted in a failure in the resulting digital signature.
9. The IC of claim 8 , further comprising:
a tuning circuit to adjust a source of the first signal based on the characterized parameter.
10. The IC of claim 8 , further comprising:
a calibration circuit to adjust an operation of a circuit having the first signal as an input based on the characterized parameter.
11. A computer readable storage medium storing code that is operable to manipulate at least one computer system to perform a portion of a process to fabricate an integrated circuit (IC), the IC comprising:
a programmable delay circuit to introduce a programmable delay to a first signal to generate a first delayed signal;
a digital delay line (DDL) comprising:
a first delay chain of delay elements having input to receive the first delayed signal; and
a set of storage elements, each storage element having an input coupled to an output of a corresponding delay element of the first delay chain, and an output to provide a corresponding bit of a digital reading; and
a controller to adjust the programmable delay of the programmable delay circuit based on a combination of the corresponding bits of the digital reading.
12. The computer readable storage medium of claim 11 , wherein the programmable delay circuit comprises:
a series of fixed delay stages having an input to receive the first signal; and
a multiplexer comprising:
a plurality of inputs, each input coupled to an output of a corresponding fixed delay stage of the series of fixed delay stages;
an output to provide the first delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a control signal from the controller.
13. The computer readable storage medium of claim 11 , wherein the programmable delay circuit comprises:
a series of fixed delay stages having an input to receive the first signal;
a first multiplexer comprising:
a plurality of inputs, each input coupled to an output of a corresponding fixed delay stage of the series of fixed delay stages;
an output to provide an intermediate delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a first control signal from the controller;
a second delay chain of delay elements having an input coupled to the output of the first multiplexer; and
a second multiplexer comprising:
a plurality of inputs including an input coupled to the output of the first multiplexer and inputs coupled to outputs of corresponding delay elements of the second delay chain;
an output to provide the first delayed signal; and
a control input to switch the output among the plurality of inputs responsive to a second control signal from the controller.
14. The computer readable storage medium of claim 11 , wherein the IC further comprises:
a decoder to generate a digital signature from the digital reading; and
wherein the controller is to iteratively adjust the programmed delay of the programmable delay circuit to search for a failure in a resulting digital signature.
15. The computer readable storage medium of claim 14 , wherein the IC further comprises:
a characterization circuit to characterize a parameter of the first signal based on the programmed delay that resulted in a failure in the resulting digital signature.
16. The computer readable storage medium of claim 11 , wherein the first signal is a clock signal.
17. The computer readable storage medium of claim 11 , wherein the set of storage elements comprises a set of flip-flops, each flip flop comprising a clock input to receive a clock signal.