Metal gate with silicon sidewall spacers

1. A method comprising:

forming an opening in a dielectric to reveal a protruding semiconductor fin;

forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin;

forming a conductive diffusion barrier layer over the gate dielectric, wherein the conductive diffusion barrier layer extends into the opening;

forming a silicon layer over the conductive diffusion barrier layer and extending into the opening;

performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer; and

after the dry etch, forming a conductive layer over the conductive diffusion barrier layer and extending into the opening.

2. The method of claim 1 , wherein the dry etch is anisotropic.

3. The method of claim 1 , wherein the dry etch is performed with a process gas comprising an etching gas and a deposition gas.

4. The method of claim 3 , wherein the deposition gas comprises a carbon-and-hydrogen containing gas.

5. The method of claim 1 further comprising, after the dry etch and before the conductive layer is formed, performing a wet etch to remove a polymer formed in the dry etch, wherein the polymer is deposited at bottom corners of the opening.

6. The method of claim 1 , wherein after the dry etch, the silicon layer comprises a silicon corner spacer remaining at a bottom corner of the opening.

7. The method of claim 6 , wherein the conductive diffusion barrier layer and the conductive layer are both in physical contact with the silicon corner spacer.

8. A method comprising:

removing a dummy gate stack to form an opening in an inter-layer dielectric;

forming a gate dielectric on sidewalls and a top surface of a protruding semiconductor fin in the opening;

forming a conductive diffusion barrier layer over the gate dielectric, wherein the conductive diffusion barrier layer extends into the opening;

forming a polysilicon layer over the conductive diffusion barrier layer and extending into the opening;

performing an anneal on the polysilicon layer and the gate dielectric;

after the anneal, performing an anisotropic etch on the polysilicon layer to form a polysilicon corner spacer at a corner of the opening, wherein a polymer is formed to cover the polysilicon corner spacer;

etching the polymer, with the polysilicon corner spacer remaining after the etching; and

after the anisotropic etch, forming a conductive layer over the conductive diffusion barrier layer and the polysilicon corner spacer.

9. The method of claim 8 , wherein after the anisotropic etch and the etching the polymer, horizontal portions and vertical portions of the polysilicon layer are removed, and a top surface and a sidewall surface of the conductive diffusion barrier layer are exposed, with the top surface and the sidewall surface of the conductive diffusion barrier layer being in the opening.

10. The method of claim 8 , wherein the conductive diffusion barrier layer and the conductive layer are both in physical contact with the polysilicon corner spacer.

11. The method of claim 8 , wherein the conductive diffusion barrier layer and the conductive layer are in physical contact with each other.

12. The method of claim 8 , wherein the anisotropic etch is a dry etch, and the etching the polymer is performed using a wet etch.

13. The method of claim 8 , wherein the polysilicon corner spacer is undoped with p-type and n-type impurities.

14. A method comprising:

removing a dummy gate stack to form an opening in a dielectric layer, with a first semiconductor fin and a second semiconductor fin in the opening being exposed;

forming a gate dielectric extending into the opening, wherein the gate dielectric is on sidewalls and top surfaces of the first and the second semiconductor fins;

forming a first polysilicon corner spacer at a first corner between the first semiconductor fin and a bottom surface of the opening, and a second polysilicon corner spacer at a second corner between the second semiconductor fin and the bottom surface of the opening, wherein each of the first polysilicon corner spacer and the second polysilicon corner spacer comprises a portion between the first and the second semiconductor fins, and the first polysilicon corner spacer and the second polysilicon corner spacer are separated from each other; and

forming a conductive layer over the first polysilicon corner spacer and the second polysilicon corner spacer to form a gate electrode for a Fin Field-Effect Transistor (FinFET).

15. The method of claim 14 further comprising forming a conductive diffusion barrier layer over the gate dielectric, wherein the first polysilicon corner spacer and the second polysilicon corner spacer are over the conductive diffusion barrier layer.

16. The method of claim 15 , wherein the conductive diffusion barrier layer and the conductive layer are both in physical contact with the first polysilicon corner spacer and the second polysilicon corner spacer.

17. The method of claim 15 , wherein the conductive diffusion barrier layer and the conductive layer are in physical contact with each other.

18. The method of claim 14 , wherein the first polysilicon corner spacer and the second polysilicon corner spacer are formed by:

forming a polysilicon layer over the gate dielectric, with the polysilicon layer extending into the opening; and

etching the polysilicon layer.

19. The method of claim 18 further comprising performing an anneal on the polysilicon layer and the gate dielectric.

20. The method of claim 14 , wherein the first polysilicon corner spacer and the second polysilicon corner spacer are not doped with p-type and n-type impurities.