Efficient reduction of read disturb errors
Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.
1. A memory system comprising:
a non-volatile memory space organized into a plurality of blocks, each block comprising a plurality of pages, and each page defining an individually addressable physical memory location; and
a controller operatively coupled to the non-volatile memory space and configured to:
access a logical-to-physical translation table that associates a logical address provided in a WRITE request with a physical address corresponding to a page within the non-volatile memory space;
accumulate a Block READ Count corresponding to the number of times any of the pages in a first block have been read;
determine whether a page with the first block has been corrupted as a result of an error other than a READ disturb error;
set the Block READ Count at a predetermined number if a page with the first block has been corrupted as a result of an error other than a READ disturb error; and
respond to a plurality of READ requests for pages within the first block received after the Block READ Count has reached the predetermined number, such response comprising:
moving data associated with a requested page to a page in a second block that is different from the first block, without moving data associated with other pages in the first block to a different block, and
modifying the logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.
2. The memory system of claim 1 wherein the controller is configured to initialize the Block READ Count for at least one block at a number other than zero.
3. The memory system of claim 1 wherein the controller is further configured to determine whether the Block READ Count has reached the predetermined number by determining whether the Block READ Count has exceeded a number.
4. The memory system of claim 1 wherein the controller is configured to maintain a Block READ Count for each block of memory within the non-volatile memory space.
5. The memory system of claim 1 wherein the controller is configured to associate a plurality of blocks together in a block group, and wherein the controller is further configured to accumulate a block group READ count corresponding to a request for a page within any block within the block group.
6. The memory system of claim 1 wherein the controller is configured to provide an indication that a page within the first block no longer contains valid data upon the movement of the data associated with the page to a page in the second block.
7. The memory system of claim 1 wherein the non-volatile memory space comprises a plurality of non-volatile memory chips and wherein the controller is configured such that both the first block and the second block are within the same non-volatile memory chip.