IP Library Granted Patent US 9,502,252
Granted Patent B2
US 9,502,252 · App. 14/637,400 · Granted Nov 22, 2016

Semiconductor device and method for fabricating the same

Inventors: Li-Wei Feng (Kaohsiung, TW); Shih-Hung Tsai (Tainan, TW); Chao-Hung Lin (Changhua County, TW); Hon-Huei Liu (Kaohsiung, TW); Shih-Fang Hong (Tainan, TW); Jyh-Shyang Jenq (Pingtung County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/2256H01L21/324H01L21/823814H01L21/823821H01L27/0924
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Quick Facts
Patent No.
US 9,502,252
App. No.
14/637,400
Granted
Nov 22, 2016
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

Claims (18)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having at least one fin-shaped structure thereon and a hard mask on the fin-shaped structure, wherein the fin-shaped structure comprises a top portion and a bottom portion;

forming a second liner on the top portion and the bottom portion of the fin-shaped structure, wherein a top surface of the second liner contacts a bottom surface of the hard mask; and

forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

2. The method of claim 1 , further comprising:

forming the doped layer on the fin-shaped structure;

forming the first liner on the doped layer;

forming a dielectric layer on the first liner and around the bottom portion of the fin-shaped structure; and

removing the doped layer and the first liner around the top portion of the fin-shaped structure.

3. The method of claim 2 , further comprising:

forming the dielectric layer on the first liner;

removing part of the dielectric layer so that the top surface of the dielectric layer is between the top portion and the bottom portion of the fin-shaped structure; and

removing the doped layer and the first liner to expose the top portion of the fin-shaped structure.

4. The method of claim 2 , further comprising performing an annealing process on the first liner and the doped layer around the bottom portion of the fin-shaped structure after removing the doped layer and the first liner from the top portion of the fin-shaped structure.

5. The method of claim 1 , wherein the doped layer comprises borosilicate glass (BSG) or phosphosilicate glass (PSG).

6. The method of claim 1 , further comprising forming the hard mask on the fin-shaped structure before forming the doped layer.

7. The method of claim 1 , further comprising forming the second liner on the top portion and the bottom portion of the fin-shaped structure before forming the doped layer.

8. The method of claim 7 , wherein the first liner comprises silicon nitride and the second liner comprises silicon oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2015
From: FENG, LI-WEI; TSAI, SHIH-HUNG; LIN, CHAO-HUNG; LIU, HON-HUEI; HONG, SHIH-FANG; JENQ, JYH-SHYANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 035080/0516 →
Priority Claims (1)
CN 2015 1 0062339 · Feb 6, 2015 · national
Continuity (1)
Related Publication 20160233088A1 · Aug 11, 2016