IP Library Granted Patent US 9,507,688
Granted Patent B2
US 9,507,688 · App. 14/068,652 · Granted Nov 29, 2016

Execution history tracing method

Inventors: Shuhei Sato (Kawasaki, JP); Takashi Sato (Kawasaki, JP)
Assignee: Cypress Semiconductor Corporation
G06F11/3466G06F11/3471G06F11/3636G06F11/3648G06F11/3656
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Quick Facts
Patent No.
US 9,507,688
App. No.
14/068,652
Filed
Oct 31, 2013
Granted
Nov 29, 2016
Kind
B2
Examiner
KO, CHAE M
Art Unit
2114
USPC
714/45
Abstract

An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.

Claims (29)

1. A method, comprising:

recording trace information about a tracing target during a first instruction execution cycle in a buffer;

grouping the recorded trace information with additional trace information recorded during a second instruction execution cycle, wherein the additional trace information corresponds to the tracing target; and

generating a single instruction notation for the first and second execution cycles based on the grouped recorded trace information and the additional trace information.

2. The method of claim 1 , further comprising storing the instruction notation in a trace list.

3. The method of claim 1 , further comprising obtaining a program counter value for the recorded trace information.

4. The method of claim 1 , further comprising determining that the tracing target relates to a branch instruction.

5. The method of claim 4 , wherein recording trace information comprises recording a branch factor and a branch destination program counter.

6. The method of claim 1 , further comprising determining that the tracing target relates to a write access.

7. The method of claim 6 , wherein recording trace information comprises recording an access size, and access address, and write data.

8. The method of claim 1 , further comprising determining that the tracing target relates to a read access.

9. The method of clam 8 , wherein recording trace information comprises recording an access size, an access address, and a read access ID.

10. The method of claim 1 , wherein recording the trace information comprises recording the trace information in a buffer that has a bit width capable of storing all information that may be produced in one cycle.

11. The method of claim 1 , wherein the instruction notation is configured to identify an instruction corresponding to the tracing target and one or more parameters of the instruction.

12. A system, comprising;

a buffer; and

a controller configured to:

record trace information about a tracing target during a first instruction execution cycle in the buffer;

group the recorded trace information with additional trace information recorded during a second instruction execution cycle, wherein the additional trace information corresponds to the tracing target; and

generate a single instruction notation for the first and second execution cycles based on the grouped recorded trace information and the additional trace information.

13. The system of claim 12 , wherein the controller is further configured to store the instruction notation in a trace list.

14. The system of claim 12 , wherein the controller is further configured to obtain a program counter value for the recorded trace information.

15. The system of claim 12 , wherein the controller is further configured to determine that the tracing target relates to a branch instruction.

16. The system of claim 15 , wherein the controller is configured to record the trace information by recording a branch factor and a branch destination program counter.

17. The system of claim 12 , wherein the controller is further configured to determine that the tracing target relates to a write access.

18. The system of claim 17 , wherein the controller is configured to record trace information by recording an access size, and access address, and write data.

19. The system of claim 12 , wherein the controller is further configured to determine that the tracing target relates to a read access.

20. The system of clam 19 , wherein the controller is further configured to record trace information by recording an access size, an access address, and a read access ID.

21. The system of claim 12 , wherein the buffer has a width capable of storing all information that may be produced in one cycle.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 050829/0230 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Sep 26, 2019
From: MUFG UNION BANK, N.A., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 050500/0112 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035884/0410 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2014
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 032767/0619 →
CHANGE OF NAME Recorded Apr 28, 2014
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 032773/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2014
From: SATO, SHUHEI; SATO, TAKASHI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 032766/0314 →
Priority Claims (1)
JP 2009-063164 · Mar 16, 2009 · national
Continuity (2)
Continuation 12721667 · Mar 11, 2010
Related Publication 20140075249A1 · Mar 13, 2014