Wireless transceiver circuit with reduced area
A wireless power transmission/reception system includes a wireless power transmission circuit and a wireless power reception circuit. The wireless power transmission circuit includes an oscillator, a DC-AC converter that converts a direct current to an alternating current and is turned on/off in response to a control signal, a power transmission coil that transmits AC power, a signal reception coil, and a signal receiver that transfers the control signal to the DC-AC converter. The wireless power reception circuit includes a power reception coil, a rectifier that converts an alternating current to a direct current and is turned on or off in response to the control signal, an control signal generator that generates the control signal, a signal transmission coil, and a signal transmitter that transmits the control signal through the signal transmission coil.
1. A wireless transceiver circuit comprising:
a coil having a first terminal and a second terminal; and
a transmission circuit coupled to the first and second terminals,
wherein the transmission circuit comprises:
a first pull-up driver configured to source a current to the first terminal;
a first pull-down driver configured to sink a current from the first terminal;
a second pull-up driver configured to source a current to the second terminal;
a second pull-down driver configured to sink a current from the second terminal; and
a controller, wherein the controller is configured to:
when a first transmission operation is performed, activate the first pull-up driver and the second pull-down driver;
when a second transmission operation is performed, activate the second pull-up driver and the first pull-down driver; and
when a reception operation is performed, activate the first pull-up driver, the first pull-down driver, the second pull-up driver, and the second pull-down driver to supply a bias voltage to the first and second terminals.
2. The wireless transceiver circuit of claim 1 , further comprising:
a reception circuit configured to detect a voltage change across the first terminal and the second terminal, and to restore reception data according to the voltage change.
3. The wireless transceiver circuit of claim 2 , wherein the reception circuit comprises:
a differential amplifier configured to amplify a voltage difference between the first terminal and the second terminal; and
a differential latch configured to restore the reception data based on signals of positive and negative output terminals of the differential amplifier.
4. The wireless transceiver circuit of claim 2 , wherein the reception circuit comprises:
a differential latch configured to latch voltage changes of the first terminal and the second terminal to restore the reception data.
5. The wireless transceiver circuit of claim 4 , wherein the reception circuit further comprises:
a differential amplifier configured to amplify the reception data based on a voltage difference between positive and negative output terminals of the differential latch.
6. The wireless transceiver circuit of claim 1 , wherein the first or second transmission operation is performed when a logic level of a signal to be transmitted changes.
7. The wireless transceiver circuit of claim 1 , wherein:
the first pull-up driver includes a first PMOS transistor for supplying a high voltage to the first terminal in response to a first pull-up driving signal;
the first pull-down driver includes a first NMOS transistor for supplying a low voltage to the first terminal in response to a first pull-down driving signal;
the second pull-up driver includes a second PMOS transistor for supplying the high voltage to the second terminal in response to a second pull-up driving signal; and
the second pull-down driver includes a second NMOS transistor for supplying the low voltage to the second terminal in response to a second pull-down driving signal.