Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
1. A method comprising:
providing a relaxed SiGe layer on a substrate;
forming a strained SiGe layer over said relaxed SiGe layer;
forming a Si layer over said strained SiGe layer;
forming a gate stack directly over said Si layer, said gate stack defining a channel region, said channel region comprising at least a portion of said strained SiGe layer; and
providing at least one region adjacent said channel region and gate stack, said at least on region comprising at least one of silicide and silicide/germanicide disposed over said relaxed SiGe layer.
2. The method of claim 1 , wherein the step of providing at least one region comprising at least one of silicide and silicide/germanicide comprises:
providing a metal layer over at least a portion of said relaxed SiGe layer; and
reacting said metal layer with at least one of said portion of said relaxed SiGe layer and said strained SiGe layer.
3. The method of claim 2 , wherein said metal layer comprises at least one of Ti, Co, and Ni.
4. The method of claim 1 , further comprising planarizing said relaxed SiGe layer prior to providing said strained SiGe layer.
5. The method of claim 1 , further comprising forming a SiGe spacer layer directly over said strained SiGe layer, said Si layer being directly over said SiGe spacer layer.
6. The method of claim 1 , wherein said at least on region comprises silicide and silicide/germanicide disposed over said relaxed SiGe layer.
7. A method comprising:
providing a relaxed SiGe layer having a first Ge concentration on a substrate, and, thereover, at least one strained device layer;
providing a protective SiGe layer having a second Ge concentration higher than the first Ge concentration over said at least one strained device layer;
providing a Si precursor layer directly over said protective SiGe layer; and
reacting said Si precursor layer with a metal thereby forming at least one region comprising a silicide phase.
8. The method of claim 7 , wherein said protective SiGe layer is substantially strained.
9. The method of claim 7 , wherein said protective SiGe layer is substantially relaxed.
10. The method of claim 9 , wherein said Si precursor layer has a thickness beyond its critical thickness.
11. The method of claim 7 , wherein the metal comprises at least one of Ti, Co, and Ni.
12. The method of claim 7 , wherein said at least one strained device layer is a strained Si layer.
13. The method of claim 7 , wherein said at least one strained device layer comprises at least one of Si, SiGe, and Ge.
14. The method of claim 7 , wherein said relaxed SiGe layer is planarized.
15. The method of claim 7 , further comprising forming a gate stack disposed over said at least one strained device layer, said gate stack defining a channel region, said channel region comprising at least a portion of said at least one strained device layer.
16. A method comprising:
forming a strained Si region over a relaxed SiGe region;
forming a SiGe region over the strained Si region; and
reacting said strained Si region and said SiGe region with a metal thereby forming at least one contact region comprising silicide and silicide/germanicide.
17. The method of claim 16 , wherein the metal comprises at least one of Ti, Co, and Ni.
18. The method of claim 16 , wherein said SiGe region is substantially strained.
19. The method of claim 16 , wherein said SiGe region exceeds its critical thickness.
20. The method of claim 16 , further comprising forming a gate stack disposed over said strained Si region, said gate stack defining a channel region, said channel region comprising at least a portion of said strained Si region.