Method for fabricating electronic device with variable resistance material layer

1. A method for fabricating an electronic device including a semiconductor memory, comprising:

forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate;

forming a bottom electrode in a portion of the opening to have an exposed top surface;

forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode;

forming a top electrode over the variable resistance material layer so as to fill the opening;

etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode and including a sidewall portion of the variable resistance material layer; and

removing the part of the variable resistance material layer to form a unit cell.

2. The method of claim 1 , wherein the variable resistance material layer has a horizontal part and a vertical part, and

the etching of the first interlayer dielectric layer includes etching the first interlayer dielectric layer to a level corresponding to the surface of the horizontal part of the variable resistance material layer.

3. The method of claim 1 , wherein the removing of the part of the variable resistance material layer includes performing a dry etching process or wet cleaning process.

4. The method of claim 3 , wherein the dry etching process comprises an IBE (Ion Beam Etching) process.

5. The method of claim 4 , wherein the IBE process is performed at a tilt of 30° to 90°.

6. The method of claim 1 , wherein the variable resistance material layer comprises a transition metal oxide, a metal oxide including a perovskite-based material, a phase-change material including a chalcogenide-based material, a ferrodielectric material, or a ferromagnetic material.

7. The method of claim 1 , further comprising, after the removing of the part of the variable resistance material layer:

forming a spacer layer along the entire structure including the top electrode;

forming a second interlayer dielectric layer over the spacer layer;

etching the second interlayer dielectric layer to expose the top electrode; and

forming a conductive line over the top electrode to be in contact with the top electrode.