Adaptable rate transceiver
A transceiver integrated circuit (IC) receives signals having a mix of idle characters and data via a multi-lane system-side signaling interface at a first signaling rate compliant with a standards-based signaling protocol. The transceiver IC outputs signals via a multi-lane line-side signaling interface at a second signaling rate that is lower than the first signaling rate and non-compliant with the standards-based signaling protocol and also outputs one or more requests to a remote IC source of the signals received via the system-side signaling interface to adjust a proportion of idle characters within the received signals as necessary to balance a data rate of the received signals with the second signaling rate without adjusting the first signaling rate.
1. A transceiver integrated circuit (IC) comprising:
a system-side signaling interface having a plurality of system-side signaling lanes and transceiver circuitry to receive and output signals via the system-side signaling lanes at one or more standards-based signaling rates specified by an industry interoperability standard;
a line-side signaling interface having a plurality of line-side signaling lanes and transceiver circuitry to receive and output signals via the line-side signaling lanes at one or more signaling rates non-compliant with the standards-based signaling rates, the signals received via the line-side signaling lanes including information to be conveyed in the signals output via the system-side signaling lanes, and the signals received via the system-side signaling lanes including information to be conveyed in the signals output via the line-side signaling lanes; and
wherein the transceiver circuitry to receive and output signals via the line-side signaling lanes at one or more signaling rates non-compliant with the standards-based signaling rates comprises circuitry to incrementally adjust the signaling rate of the signals received and output via the line-side signaling lanes over a time interval during which the signals received and output via the system-side signaling lanes are received and output at a fixed standards-based signaling rate.
2. The transceiver IC of claim 1 wherein at least one of the system-side signaling interface and the line-side signaling interface comprises an optical signaling interface.
3. The transceiver IC of claim 1 wherein at least one of the system-side signaling interface and the line-side signaling interface comprises an electrical signaling interface.
4. The transceiver IC of claim 1 wherein at least one of modulation or encoding of the signals output via the line-side signaling interface is non-compliant with the industry interoperability standard that specifies the one or more standards-compliant signaling rates.
5. The transceiver IC of claim 1 wherein the signals received and output via the line-side signaling interface constitute packetized information conveyed in discrete frames, and wherein a format of the discrete frames is non-compliant with the industry interoperability standard that specifies the one or more standards-compliant signaling rates.
6. The transceiver IC of claim 5 wherein a minimum hamming distance of all possible transmitted frames is substantially different from a minimum hamming distance of all possible frames transmitted in accordance with industry interoperability standard.
7. A transceiver integrated circuit (IC) comprising:
a system-side signaling interface having a plurality of system-side signaling lanes and transceiver circuitry to receive and output signals via the system-side signaling lanes at one or more standards-based signaling rates specified by an industry interoperability standard;
a line-side signaling interface having a plurality of line-side signaling lanes and transceiver circuitry to receive and output signals via the line-side signaling lanes at one or more signaling rates non-compliant with the standards-based signaling rates, the signals received via the line-side signaling lanes including information to be conveyed in the signals output via the system-side signaling lanes, and the signals received via the system-side signaling lanes including information to be conveyed in the signals output via the line-side signaling lanes; and
wherein the line-side signaling interface implements forward error correction with a substantially different encoding gain than a forward error correction implemented by the system-side signaling interface.
8. A transceiver integrated circuit (IC) comprising:
a system-side signaling interface having a plurality of system-side signaling lanes and transceiver circuitry to receive and output signals via the system-side signaling lanes at one or more standards-based signaling rates specified by an industry interoperability standard;
a line-side signaling interface having a plurality of line-side signaling lanes and transceiver circuitry to receive and output signals via the line-side signaling lanes at one or more signaling rates non-compliant with the standards-based signaling rates, the signals received via the line-side signaling lanes including information to be conveyed in the signals output via the system-side signaling lanes, and the signals received via the system-side signaling lanes including information to be conveyed in the signals output via the line-side signaling lanes; and
data transfer equalization logic that adjusts an effective data transfer rate of the signals received and output via the system-side signaling lanes according to a bandwidth of a signaling channel to which the line-side signaling lanes are to be coupled.
9. The transceiver IC of claim 8 wherein the data transfer equalization logic substantially equalizes average non-idle data signaling rates of the system-side and line-side signaling interfaces.
10. A method of operation within a transceiver integrated circuit (IC) having a system-side signaling interface and a line-side signaling interface, the method comprising:
receiving and outputting signals via constituent system-side signaling lanes of the system-side signaling interface at one or more standards-based signaling rates specified by an industry interoperability standard;
receiving and outputting signals at one or more non-standards-compliant signaling rates via constituent line-side signaling lanes of the line-side signaling interface, including receiving information via the line-side signaling lanes to be conveyed in the signals output via the system-side signaling lanes and conveying information received via the system-side signaling lanes in the signals output via the line-side signaling lanes; and
wherein receiving and outputting signals via the line-side signaling lanes at one or more signaling rates non-compliant with the standards-based signaling rates comprises incrementally adjusting the signaling rate of the signals received and output via the line-side signaling lanes over a time interval during which the signals received and output via the system-side signaling lanes are received and output at a fixed standards-based signaling rate.
11. The method of claim 10 wherein at least one of the system-side signaling interface and the line-side signaling interface comprises an optical signaling interface.
12. The method of claim 10 wherein at least one of the system-side signaling interface and the line-side signaling interface comprises an electrical signaling interface.
13. The method of claim 10 wherein at least one of modulation or encoding of the signals output via the line-side signaling interface is non-compliant with the industry interoperability standard that specifies the one or more standards-compliant signaling rates.
14. The method of claim 10 wherein the signals received and output via the line-side signaling interface constitute packetized information conveyed in discrete frames, and wherein a format of the discrete frames is non-compliant with the industry interoperability standard that specifies the one or more standards-compliant signaling rates.
15. The method of claim 14 wherein a minimum hamming distance of all possible transmitted frames is substantially different from a minimum hamming distance of all possible frames transmitted in accordance with the industry interoperability standard.
16. A method of operation within a transceiver integrated circuit (IC) having a system-side signaling interface and a line-side signaling interface, the method comprising:
receiving and outputting signals via constituent system-side signaling lanes of the system-side signaling interface at one or more standards-based signaling rates specified by an industry interoperability standard;
receiving and outputting signals at one or more non-standards-compliant signaling rates via constituent line-side signaling lanes of the line-side signaling interface, including receiving information via the line-side signaling lanes to be conveyed in the signals output via the system-side signaling lanes and conveying information received via the system-side signaling lanes in the signals output via the line-side signaling lanes; and
implementing forward error correction within the line-side and system-side signaling interfaces, including implementing forward error correction within the line-side signaling interface with a substantially different encoding gain than in the forward error correction implemented within the system-side signaling interface.
17. A method of operation within a transceiver integrated circuit (IC) having a system-side signaling interface and a line-side signaling interface, the method comprising:
receiving and outputting signals via constituent system-side signaling lanes of the system-side signaling interface at one or more standards-based signaling rates specified by an industry interoperability standard;
receiving and outputting signals at one or more non-standards-compliant signaling rates via constituent line-side signaling lanes of the line-side signaling interface, including receiving information via the line-side signaling lanes to be conveyed in the signals output via the system-side signaling lanes and conveying information received via the system-side signaling lanes in the signals output via the line-side signaling lanes; and
adjusting an effective data transfer rate of the signals received and output via the system-side signaling lanes according to a bandwidth of a signaling channel to which the line-side signaling lanes are coupled, including equalizing average non-idle data signaling rates of the system-side and line-side signaling interfaces.
18. The transceiver IC of claim 1 wherein the industry interoperability standard is an Ethernet standard.
19. The method of claim 10 wherein the industry interoperability standard is an Ethernet standard.