Semiconductor device and fabricating method thereof
A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate. The gate stack is disposed over the substrate to overlay a channel region between the first and second S/D regions. The gate stack includes a gate dielectric layer disposed over the substrate; and a metal alloy disposed on the gate dielectric layer and configured as a filling layer in the gate stack; wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.
1. A semiconductor device comprising:
a substrate;
a first and second source/drain regions on the substrate; and
a gate stack disposed over the substrate to overlay a channel region between the first and second S/D regions, the gate stack comprising:
a gate dielectric layer, disposed over the substrate;
a metal alloy, disposed on the gate dielectric layer and configured as a filling layer in the gate stack;
a work function layer, disposed over the gate dielectric layer;
a blocking layer, disposed over the work function layer; and
a wetting layer, disposed over the blocking layer;
wherein the metal alloy is disposed over the wetting layer, and the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.
2. The semiconductor device of claim 1 , wherein the metal alloy comprises a percentage of silicon at least about 0.2%.
3. The semiconductor device of claim 2 , wherein the first corrosion resistance is higher than a second corrosion resistance of a metal alloy without the silicon.
4. The semiconductor device of claim 2 , wherein the metal alloy further comprises a percentage of copper at least about 0.5%.
5. The semiconductor device of claim 1 , wherein the metal alloy comprises a first alloying component of silicon, a second alloying component of copper, and third alloying component of aluminum.
6. The semiconductor device of claim 1 , wherein the gate dielectric layer surrounds the metal alloy.
7. The semiconductor device of claim 1 , wherein the gate stack further comprises:
a capping layer, disposed between the gate dielectric layer and the work function layer.
8. The semiconductor device of claim 1 , wherein the gate stack further comprises:
a non-conductive spacer, configured to be a side wall of the gate stack.
9. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first and second source/drain (S/D) regions on the substrate; and
forming a gate stack over the substrate to overlay a channel region between the first and second S/D regions, comprising:
forming a gate dielectric layer over the substrate; and
forming a metal alloy on the gate dielectric layer to be a filling layer in the gate stack;
wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer, and forming the metal alloy includes sputtering an Al—Si—Cu target.
10. The method of claim 9 , further comprising forming a dielectric around the gate stack.
11. The method of claim 9 , further comprising forming a contact opening adjacent to the gate stack, wherein the contact opening exposes the first and second source/drain (S/D) regions.
12. The method of claim 11 , further comprising flowing the etchant into the contact opening to remove the carbon-containing polymer.
13. The method of claim 9 , wherein the first corrosion resistance is higher than a second corrosion resistance of a metal alloy without the silicon.
14. The method of claim 8 , further comprising:
forming a non-conductive spacer to be a side wall of the gate stack.
15. The method of claim 8 , wherein forming the gate stack over the substrate to overlay the channel region between the first and second S/D regions further comprises:
forming a work function layer over the gate dielectric layer;
forming a blocking layer over the work function layer; and
forming a wetting layer over the blocking layer;
wherein the metal alloy is disposed over the wetting layer.
16. The method of claim 15 , wherein forming the gate stack over the substrate to overlay the channel region between the first and second S/D regions further comprises:
forming a capping layer in between the gate dielectric layer and the work function layer.
17. The method of claim 9 , wherein the gate stack is formed in an interlayer dielectric layer (ILD) disposed on the substrate, and the method further comprises:
etching the ILD to form a contact opening to expose one of the first and second source/drain (S/D) regions by using the etchant.
18. The method of claim 17 , wherein the method further comprises:
forming a contact in the contact opening to couple to the one of the first and second source/drain (S/D) regions.
19. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first and second source/drain (S/D) regions on the substrate; and
forming a gate stack over the substrate to overlay a channel region between the first and second S/D regions, comprising:
forming a gate dielectric layer over the substrate;
forming a metal alloy on the gate dielectric layer to be a filling layer in the gate stack;
forming a work function layer over the gate dielectric layer;
forming a blocking layer over the work function layer; and
forming a wetting layer over the blocking layer;
wherein the metal alloy is disposed over the wetting layer, and the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.