Multi-level voltage regulator system
A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.
1. A multi-level voltage regulator system comprising:
(a) input voltage detector (IVD);
(b) voltage source reference (VSR);
(c) regulation feedback comparator (RFC); and
(d) intermediate bus DC-DC converter (IBC);
wherein
said RFC comprises a positive input node, a negative input node, and a comparison output node;
said IBC comprises a voltage bus input port (VBIP), voltage bus output port (VBOP), and voltage adjust input port (VAIP);
said RFC positive input node is electrically coupled to said VSR;
said RFC negative input node is electrically coupled to said VBOP;
said RFC comparison output node is electrically coupled to said VAIP;
said IVD is configured to monitor said VBIP and generate a stepped reference voltage (SRV) to the voltage detected at said VBIP;
said SRV modulates the comparison behavior of said RFC by adjusting the voltage at said positive input node or the voltage at said negative input node; and
said IBC is configured to modulate the voltage at said VBOP in response to the voltage at said VAIP.
2. The multi-level voltage regulator system of claim 1 wherein said IVD further comprises an input voltage hysteresis characteristic.
3. The multi-level voltage regulator system of claim 1 wherein said IVD is configured to generate a plurality of said SRV voltage levels.
4. The multi-level voltage regulator system of claim 1 wherein said IVD is configured to generate said SRV voltage levels in a continuous fashion by generating said SRV as a continuous signal proportional to said monitored VBIP voltage.
5. The multi-level voltage regulator system of claim 1 wherein said positive input node is electrically coupled to said VSR via the midpoint of a resistive divider that has terminal resistor nodes electrically coupled to said VSR and a transconducting switch controlled by said IVD.
6. The multi-level voltage regulator system of claim 1 wherein said positive input node is electrically coupled to said VSR via a resistive divider electrically shunted by a transconducting switch controlled by said IVD.
7. The multi-level voltage regulator system of claim 1 wherein said positive input node is electrically coupled to said VSR via a digital potentiometer that is controlled by said IVD.
8. The multi-level voltage regulator system of claim 1 wherein said negative input node is electrically coupled to said VBOP via a resistive divider.
9. The multi-level voltage regulator system of claim 1 wherein said negative input node is electrically coupled to said VBOP via a resistive divider electrically shunted by a transconducting switch controlled by said IVD.
10. The multi-level voltage regulator system of claim 1 wherein said negative input node is electrically coupled to said VBOP through a digital potentiometer that is controlled by said IVD.