Current sensor

1. A circuit comprising:

an inductor;

a low-frequency sensor connected to the inductor;

a high-frequency sensor connected to the inductor; and

an integrator connected to the low-frequency sensor and the high frequency sensor, comprising one or more resistive devices and one or more capacitive devices, wherein one or both of: (i) the resistance provided by the one or more resistive devices and (ii) the capacitance provided by one or more capacitive devices vary as a function of inductance of the inductor such that the integrator is characterized by a time constant that varies as a function of the inductance of the inductor.

2. The circuit of claim 1 , wherein the low-frequency sensor is an open loop Hall effect sensor, a closed loop Hall effect sensor, a flux gate sensor, a giant magneto resistance sensor, a resistive sensor, or a DC resistance sensor, and the high-frequency sensor is a sense winding.

3. The circuit of claim 1 , wherein the low-frequency sensor is a Hall effect sensor and the high-frequency sensor is a sense winding.

4. The circuit of claim 3 , wherein the integrator is characterized by a time constant that decreases when the inductance of the inductor decreases in response to an increase in an average current through the inductor.

5. The circuit of claim 4 , wherein the integrator is characterized by a time constant that decreases non-linearly when the inductance of the inductor decreases non-linearly in response to an increase in an average current through the inductor.

6. The circuit of claim 5 , wherein the integrator is characterized by a time constant that decreases proportionally with the inductance of the inductor when the inductance of the inductor decreases in response to an increase in an average current through the inductor.

7. The circuit of claim 3 , wherein at least one of the one or more capacitive devices of the integrator is a capacitor that has a capacitance that decreases as the inductance of the inductor decreases in response to an increase in an average current through the inductor.

8. The circuit of claim 7 , wherein at least one of the one or more capacitive devices of the integrator is a capacitor that has a capacitance that decreases non-linearly when the inductance of the inductor decreases non-linearly in response to an increase in an average current through the inductor.

9. The circuit of claim 8 , wherein at least one of the one or more capacitive devices of the integrator is a capacitor that has a capacitance that decreases proportionally with the inductance of the inductor when the inductance of the inductor decreases in response to an increase in an average current through the inductor.

10. The circuit of claim 3 , wherein at least one of the one or more capacitive devices of the integrator is a transistor that has a capacitance that decreases as the inductance of the inductor decreases in response to an increase in an average current through the inductor.

11. The circuit of claim 10 , wherein at least one of the one or more capacitive devices of the integrator is a transistor that has a capacitance that decreases non-linearly when the inductance of the inductor decreases non-linearly in response to an increase in an average current through the inductor.

12. The circuit of claim 11 , wherein at least one of the one or more capacitive devices of the integrator is a transistor that has a capacitance that decreases proportionally with the inductance of the inductor when the inductance of the inductor decreases in response to an increase in an average current through the inductor.

13. The circuit of claim 12 , wherein the transistor is a MOSFET.

14. The circuit of claim 12 , wherein the transistor is pre-biased by a voltage divider.

15. The circuit of claim 3 , wherein at least one of the one or more resistive devices of the integrator is a resistor has a resistance that decreases as the inductance of the inductor decreases in response to an increase in an average current through the inductor.

16. The circuit of claim 3 , wherein:

at least one of the one or more capacitive devices of the integrator has a capacitance that decreases as the inductance of the inductor decreases in response to an increase in an average current through the inductor; and

at least one of the one or more resistive devices of the integrator has a resistance that decreases as the inductance of the inductor decreases in response to an increase in an average current through the inductor.

17. The circuit of claim 3 , wherein the inductor is part of a switched-mode power supply or an amplifier.

18. The circuit of claim 3 , wherein the low-frequency sensor and the high-frequency sensor are connected in series.

19. The circuit of claim 3 , wherein

the low-frequency sensor is connected to an operational amplifier;

the high-frequency sensor is connected to the operational amplifier; and

the operational amplifier is connected to the integrator.

20. A method, comprising:

determining the inductance of an inductor for a plurality of currents through the inductor;

selecting a low-frequency sensor to output a first voltage in response to a current through the inductor;

selecting a high-frequency sensor to output a second voltage in response to the current through the inductor; and

configuring an integrator to output a third voltage in response to the first voltage and the second voltage, wherein the integrator comprises one or more resistive devices and one or more capacitive devices, and one or both of (i) the resistance provided by the one or more resistive devices and (ii) the capacitance provided by one or more capacitive devices vary as a function of the inductance such that the integrator is characterized by a time constant that varies as a function of the inductance of the inductor for the plurality of currents through the inductor.

21. The method of claim 20 , wherein configuring comprises:

selecting the one or more resistive devices; and

selecting the one or more capacitive devices such that the capacitance provided by the one or more capacitive devices varies as a function of the inductance of the inductor for the plurality of currents through the inductor.

22. The method of claim 20 , wherein configuring comprises:

selecting the one or more resistive devices such that the resistance provided by the one or more resistive devices varies as a function of the inductance of the inductor for the plurality of currents through the inductor; and

selecting the one or more capacitive devices.