IP Library Granted Patent US 9,543,196
Granted Patent B2
US 9,543,196 · App. 14/674,332 · Granted Jan 10, 2017

Methods of fabricating semiconductor devices using nanowires

Inventors: Hyun Park (Suwon-si, KR); Dong-Hyun Im (Suwon-si, KR); Soon-Gun Lee (Hwaseong-si, KR); Jong-Myeong Lee (Seongnam-si, KR); Han-Jin Lim (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/76837B82Y10/00H01L21/02532H01L21/02603H01L21/02645H01L21/02653H01L21/76802H01L21/76844H01L21/76877H01L27/10814H01L27/10817H01L27/10855H01L28/91H01L29/413
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Quick Facts
Patent No.
US 9,543,196
App. No.
14/674,332
Granted
Jan 10, 2017
Kind
B2
Abstract

Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Claims (42)

1. A method of forming a semiconductor device, the method comprising:

forming guide patterns exposing base patterns;

forming first nanowires on the base patterns by performing a first nanowire growth process;

forming a first molding insulating layer between the first nanowires;

forming holes exposing surfaces of the base patterns by removing the first nanowires; and

forming first electrodes comprising a conductive material in the holes.

2. The method of claim 1 , wherein the base patterns include at least one of poly-crystalline silicon, a metal, or a metal compound.

3. The method of claim 1 , wherein the guide patterns include silicon nitride.

4. The method of claim 1 , wherein the first nanowires include zinc oxide.

5. The method of claim 1 , wherein the first molding insulating layer includes silicon oxide.

6. The method of claim 1 , further comprising forming barrier patterns on the surfaces of the base patterns exposed in the holes.

7. The method of claim 6 , wherein the barrier patterns include a metal silicide or a metal compound.

8. The method of claim 1 , further comprising:

removing the first molding insulating layer to expose surfaces of the first electrodes;

forming a dielectric layer on the exposed surfaces of the first electrodes; and

forming a second electrode on the dielectric layer.

9. The method of claim 8 , wherein the dielectric layer is formed on surfaces of the guide patterns.

10. The method of claim 1 , further comprising:

recessing upper surfaces of the first nanowires to be lower than an upper surface of the first molding insulating layer;

forming second nanowires on the first nanowires by performing a second nanowire growth process using the first molding insulating layer as a guide; and

forming a second molding insulating layer between the second nanowires on the first molding insulating layer.

11. A method of forming a semiconductor device, the method comprising:

forming guide patterns exposing base patterns;

forming first nanowires on the base patterns;

forming a first molding insulating layer between the first nanowires;

recessing an upper surface of the first molding insulating layer to be lower than upper surfaces of the first nanowires;

forming a first supporter exposing the upper surfaces of the first nanowires and surrounding side surfaces of the first nanowires on the first molding insulating layer;

forming storage holes exposing surfaces of the base patterns by removing the first nanowires; and

forming first electrodes comprising a conductive material in the storage holes.

12. The method of claim 11 , further comprising:

recessing the upper surfaces of the first nanowires to be lower than an upper surface of the first supporter; and

forming second nanowires on the first nanowires using the first supporter as a guide.

13. The method of claim 12 , further comprising:

forming a second molding insulating layer between the second nanowires on the first supporter;

recessing an upper surface of the second molding insulating layer to be lower than upper surfaces of the second nanowires; and

forming a second supporter surrounding side surfaces of the second nanowires on the second molding insulating layer.

14. The method of claim 13 , further comprising:

forming an upper hole exposing a portion of the upper surface of the second molding insulating layer by patterning the second supporter; and

removing the second molding insulating layer through the upper hole.

15. The method of claim 14 , further comprising:

forming a lower hole exposing a portion of the upper surface of the first molding insulating layer by patterning the first supporter; and

removing the first molding insulating layer through the lower hole.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2015
From: PARK, HYUN; IM, DONG-HYUN; LEE, SOON-GUN; LEE, JONG-MYEONG; LIM, HAN-JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 035299/0623 →
Priority Claims (1)
KR 10-2014-0112589 · Aug 27, 2014 · national
Continuity (1)
Related Publication 20160064277A1 · Mar 3, 2016