High density vertical nanowire stack for field effect transistor
An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.
1. A semiconductor structure comprising:
at least one semiconductor nanowire pair located over a substrate, wherein each of said at least one semiconductor nanowire pair includes:
a lower semiconductor nanowire having a vertical cross-sectional shape of an upright triangle; and
an upper semiconductor nanowire having a vertical cross-sectional shape of an inverted triangle:
a semiconductor material source structure having a rectangular vertical cross-sectional shape adjoined to said lower semiconductor nanowire and said upper semiconductor nanowire;
a semiconductor material drain structure having another rectangular vertical cross-sectional shape adjoined to said lower semiconductor nanowire and said upper semiconductor nanowire;
a source cap material portion located on said semiconductor material source structure;
a drain cap material portion located on said semiconductor material drain structure, said source cap material portion is spaced apart from said drain cap material portion;
a raised source region in direct physical contact with a sidewall surface of each of said semiconductor material source structure and said source cap material portion and extending onto a topmost surface of said source cap material portion; and
a raised drain region in direct physical contact with a sidewall surface of each of said semiconductor material drain structure and said drain cap material portion and extending onto a topmost surface of said drain cap material portion.
2. The semiconductor structure of claim 1 , wherein an edge defining topmost points of said lower semiconductor nanowire and an edge defining bottommost points of said upper semiconductor nanowire are within a same vertical plane.
3. The semiconductor structure of claim 1 , wherein an entirety of said lower semiconductor nanowire, said upper semiconductor nanowire, said semiconductor material source structure, and said semiconductor material drain structure is single crystalline.
4. The semiconductor structure of claim 1 , wherein non-horizontal surfaces of said lower and upper semiconductor nanowires are crystallographic surfaces having Miller indices that are equivalent under lattice symmetry of a single crystalline semiconductor material of said lower and upper semiconductor nanowires.
5. The semiconductor structure of claim 1 , wherein said at least one semiconductor nanowire pair is a plurality of semiconductor nanowire pairs that are vertically spaced from one another and overlie, or underlie, one another.
6. The semiconductor structure of claim 5 , wherein each semiconductor nanowire pair among said plurality of semiconductor nanowire pairs is laterally adjoined to a first semiconductor material source portion of said semiconductor material source structure at one end and is laterally adjoined to a first semiconductor material drain portion of said semiconductor drain structure at another end, and said semiconductor structure further comprises:
at least one second semiconductor material source portion of said semiconductor material source structure located between each vertically neighboring pair of first semiconductor material source portions of said semiconductor material source structure; and
at least one second semiconductor material drain portion of said semiconductor material drain structure located between each vertically neighboring pair of first semiconductor material drain portions of said semiconductor material drain structure, wherein said at least one second semiconductor material source portion and said at least one second semiconductor material drain portion comprise a different material than said first semiconductor material source portions and said first semiconductor material drain portions.
7. The semiconductor structure of claim 6 , wherein said at least one second semiconductor material source portion and said at least one second semiconductor material drain portion are single crystalline and are epitaxially aligned to said first semiconductor material source portions and said first semiconductor material drain portions.
8. The semiconductor structure of claim 1 , further comprising a gate structure located on said substrate and including a gate dielectric and a gate electrode, wherein said gate dielectric contacts surfaces of said at least one semiconductor nanowire pair.
9. The semiconductor structure of claim 8 , wherein said upper semiconductor nanowire is vertically spaced from said lower semiconductor nanowire by a portion of said gate electrode.