Fabrication method of a transistor with improved field effect
Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.
1. A fabrication method of a field-effect transistor, comprising the following consecutive steps:
providing a substrate comprising:
a film made from first semiconductor material,
a gate dielectric covered by a gate electrode,
source and drain areas separated by the gate electrode,
a protection layer covering the gate electrode and the source and drain areas, and
an access hole to the source area and/or to the drain areas,
depositing a metallic material in the access hole of the source and/or drain areas so that the metallic material is in contact with the first semiconductor material,
depositing an electrically conducting barrier layer, said barrier layer being non-reactive with the first semiconductor material and non-reactive with the metallic material,
depositing an electric conductor on said barrier layer so as to fill said access hole, and
performing a heat treatment so that the metallic material react with the semiconductor material to form an alloy between a metallic material and the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas,
wherein the metallic material is deposited by means of selective deposition or directional deposition in a direction perpendicular to the surface of the substrate.
2. The fabrication method according to claim 1 , wherein the electric conductor presents a higher Young's modulus than a Young's modulus of the first semiconductor material.
3. The fabrication method according to claim 1 , wherein depositing the barrier layer is performed by isotropic deposition.
4. The fabrication method according to claims 1 , wherein the first semiconductor material is mainly silicon-based and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys so that the set of stresses is a set of tensile stresses of the conduction channel.
5. The fabrication method according to claim 1 , wherein the source and/or drain area is formed by a solid silicon-carbon solution and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys.
6. The fabrication method according to claim 1 , wherein the deposition results in the metallic material being deposited only on the bottom portion of the access hole of the source and drain area.
7. A fabrication method of a field-effect transistor, comprising the following consecutive steps:
providing a substrate comprising;
a film made from first semiconductor material,
a gate dielectric covered by a gate electrode,
source and drain areas separated by the gate electrode,
a protection layer covering the gate electrode and the source and drain areas, and
an access hole to the source area and/or to the drain areas,
depositing a metallic material in the access hole of the source and/or drain areas so that the metallic material is in contact with the first semiconductor material,
depositing an electrically conducting barrier layer, said barrier layer being non-reactive with the first semiconductor material and non-reactive with the metallic material,
depositing an electric conductor on said barrier layer so as to fill said access hole, and
performing a heat treatment so that the metallic material react with the semiconductor material to form an alloy between a metallic material and the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas,
the fabrication method further comprising a chemical mechanical polishing step configured to eliminate the electric conductor deposited on the protection layer and to electrically dissociate an electric conductor connected to the source area, an electric conductor connected to the drain area, and an electric conductor connected to the gate electrode.
8. The fabrication method according to claim 7 , wherein the electric conductor presents a higher Young's modulus than a Young's modulus of the first semiconductor material.
9. The fabrication method according to claim 7 , wherein depositing the barrier layer is performed by isotropic deposition.
10. The fabrication method according to claims 7 , wherein the first semiconductor material is mainly silicon-based and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys so that the set of stresses is a set of tensile stresses of the conduction channel.
11. The fabrication method according to claim 7 , wherein the source and/or drain area is formed by a solid silicon/carbon solution and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys.
12. A fabrication method of a field-effect transistor, comprising the following consecutive steps:
providing a substrate comprising:
a film made from first semiconductor material,
a gate dielectric covered by a gate electrode,
source and drain areas separated by the gate electrode,
a protection layer covering the gate electrode and the source and drain areas, and
an access hole to the source area and/or to the drain areas,
depositing a metallic material in the access hole of the source and/or drain areas so that the metallic material is in contact with the first semiconductor material,
depositing an electrically conducting barrier layer, said barrier layer being non-reactive with the fist semiconductor material and non-reactive with the metallic material,
depositing an electric conductor on said barrier layer so as to fill said access hole, and
performing a heat treatment so that the metallic material react with the semiconductor material to form an alloy between a metallic material and the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas,
the fabrication method further comprising a planarizing step of the protection layer configured so as to expose the electrode gate and wherein said access holes to the source and drain areas are formed by means of a mask which comprises a cavity extending on each side of the gate electrode.
13. The fabrication method according to claim 12 , wherein the electric conductor presents a higher Young's modulus than a Young's modulus of the first semiconductor material.
14. The fabrication method according to claim 12 , wherein depositing the barrier layer is performed by isotropic deposition.
15. The fabrication method according to claims 12 , wherein the first semiconductor material is mainly silicon-based and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys so that the set of stresses is a set of tensile stresses of the conduction channel.
16. The fabrication method according to claim 12 , wherein the source and/or drain area is formed by a solid silicon/carbon solution and the metallic material is chosen from titanium, palladium, platinum, cobalt, nickel, tantalum, molybdenum and tungsten and their alloys.