Latency-based power mode units for controlling power modes of processor cores, and related methods and systems
Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
1. A latency-based power mode unit for controlling a power mode of a processor core, comprising:
a power mode input configured to receive power mode information relative to a power level supplied to a processor core for a data access outside of the processor core, wherein the power mode information comprises:
a data access latency of accessing data from at least one data interface; and
a power mode corresponding to the at least one data interface; and
a thread workload input configured to receive workload information relative to a status of threads in the processor core;
the latency-based power mode unit configured to generate a power mode setting to set the processor core to operate in a reduced power mode if the workload information indicates that the processor core has one or more threads in pending status and no threads in active status, and the power mode information indicates the data access latency and the power mode corresponding to the at least one data interface of each of the one or more threads in pending status corresponding to the reduced power mode.
2. The latency-based power mode unit of claim 1 , further configured to provide the power mode setting to a power mode output to provide the power mode setting to a power control unit for controlling power used by the processor core.
3. The latency-based power mode unit of claim 1 , wherein the reduced power mode comprises a power collapse level.
4. The latency-based power mode unit of claim 3 , wherein the reduced power mode further comprises a reduced power level that is lower than a nominal power level and higher than the power collapse level.
5. The latency-based power mode unit of claim 1 , further configured to generate the power mode setting to set the processor core to operate in a higher power mode if the power mode information indicates a data access latency not corresponding to the reduced power mode.
6. The latency-based power mode unit of claim 5 , further configured to:
track initiation of the data access outside of the processor core; and
generate the power mode setting to set the processor core to operate in the higher power mode if the workload information indicates that the processor core has a thread scheduled to become active within a defined threshold time following the initiation of the data access outside of the processor core.
7. The latency-based power mode unit of claim 5 , further configured to:
not generate the power mode setting to set the processor core to operate in the reduced power mode if a stored previous instance of the power mode setting set the processor core to operate in the reduced power mode; and
not generate the power mode setting to set the processor core to operate in the higher power mode if the stored previous instance of the power mode setting set the processor core to operate in the higher power mode.
8. The latency-based power mode unit of claim 1 , further configured to generate the power mode setting to set the processor core to operate in a higher power mode if the workload information indicates that the processor core has at least one thread in active status.
9. The latency-based power mode unit of claim 8 , further configured to, in response to generating the power mode setting to set the processor core to operate in the higher power mode, generate an interrupt to the processor core indicating the power mode setting is set to the higher power mode.
10. The latency-based power mode unit of claim 1 , further configured to generate the power mode setting to set the processor core to operate in the reduced power mode if the workload information indicates that all threads in the processor core are inactive.
11. The latency-based power mode unit of claim 1 , wherein the latency-based power mode unit is disposed external of the processor core.
12. The latency-based power mode unit of claim 1 , wherein the latency-based power mode unit is disposed within the processor core.
13. The latency-based power mode unit of claim 1 , wherein the data access comprises:
a load from a memory resulting from a level two (L2) cache miss; or
a load from an uncacheable peripheral.
14. The latency-based power mode unit of claim 1 integrated into an integrated circuit (IC).
15. The latency-based power mode unit of claim 1 integrated into a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
16. A latency-based power mode apparatus for controlling a power mode of a processor core, comprising:
means for receiving power mode information relative to a power level supplied to a processor core for a data access outside of the processor core, wherein the power mode information comprises:
a data access latency of accessing data from at least one data interface; and
a power mode corresponding to the at least one data interface;
means for receiving workload information relative to a status of threads in the processor core; and
means for generating a power mode setting to set the processor core to operate in a reduced power mode if the workload information indicates that the processor core has one or more threads in pending status and no threads in active status, and the power mode information indicates the data access latency and the power mode corresponding to the at least one data interface of each of the one or more threads in pending status corresponding to the reduced power mode.
17. The latency-based power mode apparatus of claim 16 , further comprising a means for providing the power mode setting to a means for controlling power used by the processor core.
18. A method of controlling a power mode of a processor core using a latency-based determination, comprising:
receiving power mode information relative to a power level supplied to a processor core for a data access outside of the processor core, wherein the power mode information comprises:
a data access latency of accessing data from at least one data interface; and
a power mode corresponding to the at least one data interface;
receiving workload information relative to a status of threads in the processor core; and
generating a power mode setting to set the processor core to operate in a reduced power mode if the workload information indicates that the processor core has one or more threads in pending status and no threads in active status, and the power mode information indicates the data access latency and the power mode corresponding to the at least one data interface of each of the one or more threads in pending status corresponding to the reduced power mode.
19. The method of claim 18 , further comprising providing the power mode setting to a power control unit for controlling power used by the processor core.
20. The method of claim 18 , wherein the reduced power mode comprises a power collapse level.
21. The method of claim 20 , wherein the reduced power mode further comprises a reduced power level that is lower than a nominal power level and higher than the power collapse level.
22. The method of claim 18 , further comprising generating the power mode setting to set the processor core to operate in a higher power mode if the power mode information indicates a data access latency not corresponding to the reduced power mode.
23. The method of claim 22 , further comprising:
tracking initiation of the data access outside of the processor core; and
generating the power mode setting to set the processor core to operate in the higher power mode if the workload information indicates that the processor core has a thread scheduled to become active within a defined threshold time following the initiation of the data access outside of the processor core.
24. The method of claim 18 , further comprising generating the power mode setting to set the processor core to operate in a higher power mode if the workload information indicates that the processor core has at least one thread in active status.
25. The method of claim 24 , further comprising, in response to generating the power mode setting to set the processor core to operate in the higher power mode, generating an interrupt to the processor core indicating the power mode setting is set to the higher power mode.
26. The method of claim 18 , further comprising generating the power mode setting to set the processor core to operate in the reduced power mode if the workload information indicates that all threads in the processor core are inactive.
27. A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to:
receive power mode information relative to a power level supplied to a processor core for a data access outside of the processor core, wherein the power mode information comprises:
a data access latency of accessing data from at least one data interface; and
a power mode corresponding to the at least one data interface;
receive workload information relative to a status of threads in the processor core; and
generate a power mode setting to set the processor core to operate in a reduced power mode if the workload information indicates that the processor core has one or more threads in pending status and no threads in active status, and the power mode information indicates the data access latency and the power mode corresponding to the at least one data interface of each of the one or more threads in pending status corresponding to the reduced power mode.
28. The non-transitory computer-readable medium of claim 27 , wherein the computer executable instructions, when executed by the processor, further cause the processor to provide the power mode setting to a power control unit for controlling power used by the processor core.
29. The non-transitory computer-readable medium of claim 27 , wherein the computer executable instructions, when executed by the processor, further cause the processor to generate the power mode setting to set the processor core to operate in a higher power mode if the power mode information indicates a data access latency not corresponding to the reduced power mode.
30. The non-transitory computer-readable medium of claim 27 , wherein the computer executable instructions, when executed by the processor, further cause the processor to generate the power mode setting to set the processor core to operate in a higher power mode if the workload information indicates that the processor core has at least one thread in active status.