Memory system including cache
According to one embodiment, a memory system comprises a first storage device containing a nonvolatile semiconductor memory and a controller configured to control the first storage device. Data from a data processor is written to the first storage device, the data is written to a second storage device. The controller transmits information indicating that data to be read is absent in the first storage device to the data processor when a read error occurs, the read error disables reading of data from the first storage device in response to a read request supplied from the data processor.
1. A memory system comprising:
a first storage device comprising a nonvolatile semiconductor memory; and
a controller configured to control the first storage device,
wherein
data from a data processor is written to the first storage device, the data is written to a second storage device, and
the controller transmits information indicating that data to be read is absent in the first storage device to the processor when a read error occurs, the read error disables reading of data from the first storage device in response to a read request supplied from the data processor.
2. The system according to claim 1 , wherein the first storage device comprises at least a cache region and a management area.
3. The system according to claim 2 , wherein the controller reduces, when the first storage device contains a bad area, the cache region by storage capacity equivalent to the storage capacity of the bad area.
4. The system according to claim 2 , further comprising:
a first error correction unit configured to correct a first error in data read from the cache region; and
a second error correction unit configured to correct a second error in data read from the management area.
5. The system according to claim 4 , wherein the first error correction unit is configured to perform error correction of a first strength, and the second error correction unit is configured to perform that of a second strength stronger than the first strength.
6. The system according to claim 5 , wherein the first storage device includes a data area.
7. The system according to claim 6 , further comprising
a third error correction unit configured to correct a third error in data read from the data area, the third error correction unit performing error correction of a third strength stronger than the first strength but weaker than the second strength.
8. The system according to claim 7 , further comprising:
an error detection unit configured to detect a fourth error in data read from the first storage device based on an error detection code.
9. The system according to claim 1 , wherein the read error includes that data to read is absent in the first storage device.
10. The system according to claim 4 , wherein the read error includes that an error in the data read from the first storage device is uncorrectable by the error correction unit.
11. The system according to claim 8 , wherein the read error includes that an error is detected in data read from the first storage device by the error detection unit.
12. The system according to claim 1 , wherein the information indicating that data is absent in the first storage device is information indicating a cache miss.
13. The system according to claim 1 , which constitutes a storage array.