Semiconductor memory device with electrode connecting to circuit chip through memory array chip

1. A semiconductor memory device comprising:

an array chip including an exposed surface side, a three-dimensionally disposed plurality of memory cells, and a memory-side interconnection layer connected to the memory cells, the array chip not including a substrate;

a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit, the circuit chip being attached to the array chip with the circuit-side interconnection layer facing the memory-side interconnection layer;

a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer, and bonded to the memory-side interconnection layer and the circuit-side interconnection layer;

a pad provided in the circuit chip; and

an external connection electrode reaching the pad from the exposed surface side of the array chip.

2. The device according to claim 1 , wherein

the array chip includes:

a stacked body including a plurality of electrode layers stacked via an insulating layer;

a semiconductor body extending in a stacking direction of the stacked body in the stacked body;

a charge storage film provided between the semiconductor body and the electrode layers;

a plurality of bit lines connected to an end portion of the semiconductor body; and

a source line connected to another end portion of the semiconductor body.

3. The device according to claim 2 , wherein

the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed, and

the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape.

4. The device according to claim 3 , wherein

the bonding metal includes a plurality of bit-line lead-out sections electrically connected to the bit lines, and

the bit-line lead-out sections are disposed in a region overlapping the memory cell array region in the stacking direction.

5. The device according to claim 1 , wherein the pad is provided in a same layer as the circuit-side interconnection layer and formed of a same material as the circuit-side interconnection layer.

6. The device according to claim 1 , further comprising an insulating film provided around the bonding metal.