Vertical bipolar transistor

1. An integrated circuit, comprising:

a transistor having:

first and second conduction terminals;

a control terminal; and

a vertical stack of a first dielectric layer, a conductive layer, and a second dielectric layer separated from the first dielectric layer by the conductive layer,

the first conduction terminal of the transistor including a first semiconductor region of a first conductivity type formed in the first dielectric layer,

the control terminal of the transistor including a second semiconductor region of a second conductivity type formed in the conductive layer and directly contacting the conductive layer, and

the second conduction terminal of the transistor including a third semiconductor region of the first conductivity type formed in the second dielectric layer; and

wherein the conductive layer is a semiconductor material including dopants of the second conductivity type, and the second semiconductor region including a diffusion profile wherein lateral edges are thicker than a middle.

2. The integrated circuit of claim 1 , wherein the semiconductor regions and semiconductor materials comprise one or more of silicon, gallium arsenide, germanium, and germanium silicon.

3. The integrated circuit of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. An integrated circuit, comprising:

a transistor having;

first and second conduction terminals;

a control terminal; and

a vertical stack of a first dielectric layer, a conductive layer, and a second dielectric layer separated from the first dielectric layer by the conductive layer,

the first conduction terminal of the transistor including a first semiconductor region of a first conductivity type formed in the first dielectric layer,

the control terminal of the transistor including a second semiconductor region of a second conductivity type formed in the conductive layer and directly contacting the conductive layer, and

the second conduction terminal of the transistor including a third semiconductor region of the first conductivity type formed in the second dielectric layer;

wherein the stack of layers is formed on a surface of a semiconductor substrate, the substrate including a well having dopants of the first conductivity type underlying at least the first region; and

wherein the first semiconductor region includes a diffusion profile wherein a middle is thicker than lateral edges of the first semiconductor region.

5. The integrated circuit of claim 4 , wherein the semiconductor regions and semiconductor materials comprise one or more of silicon, gallium arsenide, germanium, and germanium silicon.

6. The integrated circuit of claim 4 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

7. A device, comprising:

an array of memory cells, the memory cells being arranged in at least one row, each memory cell including:

a data storage element;

a transistor coupled to the data storage element, the transistor having:

a first dielectric layer;

a conductive layer;

a second dielectric layer;

a first conduction terminal including a first semiconductor region of a first conductivity type formed in the first dielectric layer;

a control terminal including a second semiconductor region of a second conductivity type formed in and directly contacting the conductive layer; and

a second conduction terminal including a third semiconductor region of the first conductivity type formed in the second dielectric layer;

the conductive layer extends between and is shared with each transistor in a row and is coupled to the control terminals of all memory cells of the row; and

wherein the conductive layer is a semiconductor material including dopants of the second conductivity type, and the second semiconductor region including a diffusion profile wherein lateral edges are thicker than a middle.

8. The device of claim 7 , wherein each transistor and the corresponding data storage element are formed vertically on a substrate with the transistor formed between the data storage element and the substrate.

9. The device of claim 7 wherein each transistor and the corresponding data storage element are formed vertically on a substrate with the data storage element formed between the transistor and the substrate.

10. The device of claim 7 , further comprising:

a row decoder coupled to word lines of the array of memory cells, where the word lines are formed by the conductive layers of the memory cells in respective rows of the array; and

a column decoder coupled to bit lines of the array of memory cells, wherein each bit line is coupled to the data storage elements of a respective column of memory cells in the array.

11. The device of claim 7 wherein each of the data storage elements comprises one of a resistive storage element, a phase change memory storage element, a dynamic random access memory storage element, a static random access storage element, a magnetic memory storage element, and a ferromagnetic memory storage element.

12. The device of claim 7 wherein the semiconductor regions and semiconductor materials comprise one or more of silicon, gallium arsenide, germanium, and germanium silicon.

13. The memory cell according to claim 11 , wherein the data storage element of each memory cell is a resistive storage element including a first metal electrode, a resistive material, and a second metal electrode, and wherein one of the electrodes is coupled to the first conduction terminal of the transistor.

14. A method, comprising:

forming a transistor that includes first and second conduction terminals and a control terminal, the forming of the transistor including:

forming a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the conductive layer being a semiconductor material including dopants of a second conductivity type;

forming the first conduction terminal as a first semiconductor region of a first conductivity type in the first dielectric layer;

forming the control terminal as a second semiconductor region of the second conductivity type in the conductive layer;

forming the second conduction terminal as a third semiconductor region of the first conductivity type in the second dielectric layer;

diffusing dopants of the second conductivity type laterally from the conductive layer to form the control terminal;

forming a hole through the stack;

depositing a semiconductor material in the hole;

forming, in a semiconductor substrate, a well including dopants of the first conductivity type, the well underlying at least the first conduction terminal and the well being exposed during forming the hole through the stack; and

diffusing dopants of the first conductivity type from the well into the semiconductor material in the hole to form the first conduction terminal.

15. The method according to claim 14 , further comprising:

implanting dopants of the first conductivity type into the top surface of the semiconductor material deposited in the hole; and

diffusing these implanted dopants of the first conductivity type into the semiconductor material in the hole to form the second conduction terminal.

16. The method of claim 15 wherein depositing a semiconductor material in the hole comprises depositing in the hole one of an undoped semiconductor material and a semiconductor material doped with a dopant of the first conductivity type, and wherein the semiconductor material is one of an amorphous semiconductor material, a polycrystalline semiconductor material, and a crystalline semiconductor material.

17. The method of claim 16 wherein the first conductivity type is N-type and the second conductivity type is P-type.

18. The method of claim 14 , wherein the semiconductor material in the hole is undoped polysilicon.