Processing accelerator with queue threads and methods therefor

1. A processing accelerator, comprising:

a processor logic unit that is a single arithmetic logic unit (ALU) or a single floating point unit (FPU);

at least one load thread to be executed by the processor logic unit to determine addresses of data and reserved to perform tasks related to locating or obtaining the data or both from a non-local memory without using the data for computations unrelated to an address of the data;

at least one compute thread to be executed by the same processor logic unit and reserved to perform computations on the data found by the load thread so that the load thread and compute thread alternatively share the same one processor logic unit during context switching between the load thread and compute thread;

at least one local memory having at least one queue to store the data located by the load thread, the load thread and the compute thread operating, at least in part, due to the status of the queue so that the load thread wakes or is suspended depending, at least in part, on whether the queue is full, and the compute thread wakes or is put to sleep depending, at least in part, on whether the queue is empty; and

a plurality of input registers communicatively connected to the processor logic unit and provided to store data to be used for calculations by the processor logic unit, wherein the compute thread is to transfer the data from the queue to at least one of the input registers for use by the processor logic unit.

2. The processing accelerator of claim 1 wherein the load thread is to transmit read requests to have data obtained and placed in the queue.

3. The processing accelerator of claim 1 comprising at least one of:

a single chip processor with one or more cores, having one or more of the processor logic units, the load thread, and the compute thread, and

a card with a digital circuit to be placed on a motherboard.

4. The processing accelerator of claim 1 being mounted at a smartphone, a tablet, or a hand-held electronic device.

5. The processing accelerator of claim 1 comprising:

wherein a portion of the registers are assigned to one or more of the threads,

and

at least one of:

(a) a single chip processor with one or more cores, having one or more of the processor logic units, the load thread, and the compute thread, and

(b) a card with a digital circuit to be placed on a motherboard;

the processing accelerator being mounted at a smartphone, a tablet, or a hand-held electronic device.