Snoop filter for multi-processor system and related snoop filtering method

1. A snoop filter for a multi-processor system, comprising:

a storage device; and

a control circuit, arranged to manage at least a first-type entry and at least a second-type entry stored in the storage device; wherein the first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache; and the second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.

2. The snoop filter of claim 1 , wherein the first-type entry has a first data structure, and the second-type entry has a second data structure different from the first data structure.

3. The snoop filter of claim 2 , wherein the first-type entry with the first data structure comprises:

an address field, arranged to store a common part of K memory addresses, wherein the K memory addresses comprise the requested first memory addresses, and K is a positive integer larger than one; and

a vector field, arranged to store K indication bits, wherein the K indication bits are arranged to indicate existence of K cache lines in the first cache, respectively, and the K cache lines comprise the multiple first cache lines; and

a cache index field, arranged to indicate the first cache.

4. The snoop filter of claim 2 , wherein the multi-processor system comprises N caches, and the second-type entry with the second data structure comprises:

an address field, arranged to store a common part of M memory addresses, wherein the M memory addresses comprise at least the requested second memory address, wherein N is a positive integer larger than one and M is a positive integer larger than or equal to one;

M vector fields, corresponding to the M memory addresses, respectively, wherein each of the M vector fields comprises N indication bits arranged to indicate existence of a same cache line in the N caches, respectively.

5. The snoop filter of claim 1 , wherein the storage device comprises a plurality of configurable entries each having a same bit length; and the control circuit is further arranged to adaptively configure a first configurable entry as the first-type entry and adaptively configure a second configurable entry as the second-type entry.

6. The snoop filter of claim 1 , wherein the storage device comprises at least a first sub-storage device and a second sub-storage device, the first sub-storage device has entries in a first bit length, and the second sub-storage device has entries in a second bit length different from or equal to the first bit length; and the control circuit is further arranged to store first-type entries in the first sub-storage device and store second-type entries in the second sub-storage device.

7. The snoop filter of claim 1 , wherein the control circuit is further arranged to transfer at least a portion of the first-type entry to at least another second-type entry in the storage device.

8. The snoop filter of claim 1 , wherein the control circuit is further arranged to transfer at least a portion of the second-type entry to at least another first-type entry in the storage device.

9. The snoop filter of claim 1 , wherein the first-type entry is stored in the storage device according to one of direct-mapped entry placement, set-associative entry placement and fully-associative entry placement.

10. The snoop filter of claim 1 , wherein the second-type entry is stored in the storage device according to one of direct-mapped entry placement, set-associative entry placement and fully-associative entry placement.

11. A snoop filter for a multi-processor system, comprising:

a storage device, comprising a plurality of configurable entries; and

a control circuit, arranged to adaptively configure at least one configurable entry as at least one first-type entry with a first data structure and adaptively configure at least one configurable entry as at least one second-type entry with a second data structure different from the first data structure, wherein the at least one first-type entry and the at least one second-type entry are arranged to record statuses of cache lines available in caches of the multi-processor system.

12. A snoop filter for a multi-processor system, comprising:

a storage device; and

a control circuit, arranged to manage a plurality of entries stored in the storage device, wherein the entries are arranged to record statuses of cache lines available in caches of the multi-processor system, the entries comprise at least a first entry and a second entry, the first entry is stored in the storage device according to a first entry placement, the second entry is stored in the storage device according to a second entry placement, and the first entry placement and the second entry placement have different associativity.

13. A snoop filtering method employed by a multi-processor system, comprising:

recording at least a first-type entry in a storage device, wherein the first-type entry is configured to record information indicative of a first cache of the multi-processor system and first requested memory addresses that are associated with multiple first cache lines each being only available in the first cache; and

recording at least a second-type entry in the storage device, wherein the second-type entry is configured to record information indicative of multiple second caches of the multi-processor system and at least a second requested memory address that is associated with a second cache line being available in each of the multiple second caches.

14. The snoop filtering method of claim 13 , wherein the first-type entry has a first data structure, and the second-type entry has a second data structure different from the first data structure.

15. The snoop filtering method of claim 14 , wherein the first-type entry with the first data structure comprises:

an address field, arranged to store a common part of K memory addresses, wherein the K memory addresses comprise the requested first memory addresses, and K is a positive integer larger than one;

a vector field, arranged to store K indication bits, wherein the K indication bits are arranged to indicate existence of K cache lines in the first cache, respectively, and the K cache lines comprise the multiple first cache lines; and

a cache index field, arranged to indicate the first cache.

16. The snoop filtering method of claim 14 , wherein the multi-processor system comprises N caches, and the second-type entry with the second data structure comprises:

an address field, arranged to store a common part of M memory addresses, wherein the M memory addresses comprise at least the requested second memory address, wherein N is a positive integer larger than one and M is a positive integer larger than or equal to one; and

M vector fields, corresponding to the M memory addresses, respectively, wherein each of the M vector fields comprises N indication bits arranged to indicate existence of a same cache line in the N caches, respectively.

17. The snoop filtering method of claim 13 , wherein the storage device comprises a plurality of configurable entries each having a same bit length; and the snoop filtering method further comprises:

adaptively configuring a first configurable entry as the first-type entry; and

adaptively configuring a second configurable entry as the second-type entry.

18. The snoop filtering method of claim 13 , wherein the storage device comprises at least a first sub-storage device and a second sub-storage device, the first sub-storage device has entries in a first bit length, and the second sub-storage device has entries in a second bit length different from or equal to the first bit length; and first-type entries are stored in the first sub-storage device and second-type entries are stored in the second sub-storage device.

19. The snoop filtering method of claim 13 , further comprising:

transferring at least a portion of the first-type entry to at least another second-type entry in the storage device.

20. The snoop filtering method of claim 13 , further comprising:

transferring at least a portion of the second-type entry to at least another first-type entry in the storage device.

21. The snoop filtering method of claim 13 , wherein the first-type entry is stored in the storage device according to one of direct-mapped entry placement, set-associative entry placement and fully-associative entry placement.

22. The snoop filtering method of claim 13 , wherein the second-type entry is stored in the storage device according to one of direct-mapped entry placement, set-associative entry placement and fully-associative entry placement.

23. A snoop filtering method for a multi-processor system, comprising:

utilizing a storage device, comprising a plurality of configurable entries;

adaptively configuring at least one configurable entry as at least one first-type entry with a first data structure; and

adaptively configuring at least one configurable entry as at least one second-type entry with a second data structure different from the first data structure;

wherein the at least one first-type entry and the at least one second-type entry are arranged to record statuses of cache lines available in caches of the multi-processor system.

24. A snoop filtering method for a multi-processor system, comprising:

recording a plurality of entries in a storage device, wherein the entries are arranged to record statuses of cache lines available in caches of the multi-processor system, the entries comprise at least a first entry and a second entry, the first entry is stored in the storage device according to a first entry placement, the second entry is stored in the storage device according to a second entry placement, and the first entry placement and the second entry placement have different associativity.