Systems, apparatuses, and methods for performing a double blocked sum of absolute differences

Inventors: Elmoustapha Ould-Ahmed-Vall (Chandler, AZ); Mostafa Hagog (Kaukab, IL); Robert Valentine (Kiryat Tivon, IL); Amit Gradstein (Binyamina, IL); Simon Rubanovich (Haifa, IL); Zeev Sperber (Zichron Yackov, IL)

Assignee: Intel Corporation

G06F15/78 G06F7/544 G06F9/3001 G06F9/30036 G06F7/50 G06F9/3836 G06F9/3877 G06F2207/5442

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Quick Facts

Patent No.: US 9,582,464
App. No.: 13/992,229
Granted: Feb 28, 2017
Kind: B2

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Abstract

Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

Claims (35)

1. A method comprising:

decoding a single instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode;

executing the decoded single instruction to, on a per data lane basis, compute a sum of absolute differences (SAD) of selected quadruplets of data elements of the first and second sources, wherein the quadruplets are selected using consecutive pairs of bits of the immediate; and

storing each calculated SAD into the destination vector register, wherein the stored SADs comprise:

in a least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source,

in a second-most least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source,

in a third-most least significant position of the destination register, the stored SAD is an absolute value of a fifth-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a sixth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a seventh-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source that is added to an absolute value of a eighth-most least significant data element position of the first source minus a sixth-most least significant data element position of the second source, and

in a fourth-most least significant position of the destination register, the stored SAD is an absolute value of a fifth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a sixth-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source that is added to an absolute value of a seventh-most least significant data element position of the first source minus a sixth-most least significant data element position of the second source that is added to an absolute value of a eighth-most least significant data element position of the first source minus a seventh-most least significant data element position of the second source.

2. The method of claim 1 , wherein the data elements of the selected quadruplets of the first and second sources are byte sized.

3. The method of claim 2 , wherein the data elements of the destination register are word sized.

4. The method of claim 1 , wherein the first source operand is a vector register and the second source operand is a memory location.

5. The method of claim 1 , wherein the first and second source operands are vector registers.

6. The method of claim 1 , wherein the first and second source operands and the destination vector register operand are all of the same size selected from the group consisting of 128-bit, 256-bit, and 512-bit.

7. An article of manufacture comprising:

a non-transitory machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operands a first and second source and an immediate and specifies as its destination a single destination vector register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause on a per data lane basis, a computation of a SAD of selected quadruplets of data elements of the first and second sources and storage of each calculated SAD into the destination vector register, wherein the quadruplets are selected using consecutive pairs of bits of the immediate, wherein the stored SADs comprise:

8. The article of manufacture of claim 7 , wherein the data elements of the selected quadruplets of the first and second sources are byte sized.

9. The article of manufacture of claim 8 , wherein the data elements of the destination register are word sized.

10. The article of manufacture of claim 7 , wherein the first source operand is a vector register and the second source operand is a memory location.

11. The article of manufacture of claim 7 , wherein the first and second source operands are vector registers.

12. The article of manufacture of claim 7 , wherein the first and second source operands and the destination vector register operand are all of the same size selected from the group consisting of 128-bit, 256-bit, and 512-bit.

13. An apparatus comprising:

a hardware decoder to decode a single instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode;

execution circuitry to, on a per data lane basis, compute a SAD of selected quadruplets of data elements of the first and second sources and store each calculated SAD into the destination vector register, wherein the quadruplets are selected using consecutive pairs of bits of the immediate, wherein the stored SADs comprise:

14. The apparatus of claim 13 , wherein the data elements of the selected quadruplets of the first and second sources are byte sized.

15. The apparatus of claim 14 , wherein the data elements of the destination register are word sized.

16. The apparatus of claim 13 , wherein the first source operand is a vector register and the second source operand is a memory location.

17. The apparatus of claim 13 , wherein the first and second source operands are vector registers.

Continuity (1)

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