IP Library › Granted Patent US 9,583,513
Granted Patent B2
US 9,583,513 · App. 15/000,096 · Granted Feb 28, 2017

Display device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/124G02F1/1368G02F1/133345G02F1/136286G11C19/28H01L27/105H01L27/12H01L27/1214H01L27/1222H01L27/1251H01L27/1255H01L29/78678G02F1/13624G09G3/3677G09G3/3688G09G2300/0417G09G2320/043G09G2330/021H01L27/13H01L29/42384H01L29/78696
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Quick Facts
Patent No.
US 9,583,513
App. No.
15/000,096
Granted
Feb 28, 2017
Kind
B2
Abstract

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Claims (183)

1. A semiconductor device comprising:

a first flip-flop; and

a second flip-flop,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,

wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,

wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,

wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,

wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,

wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,

wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,

wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,

wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,

wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,

wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,

wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,

wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,

wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,

wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,

wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,

wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,

wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and

wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.

2. The semiconductor device according to claim 1 ,

wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

3. The semiconductor device according to claim 1 ,

wherein a first clock signal is input to the first wiring, and

wherein a second clock signal is input to the second wiring.

4. The semiconductor device according to claim 1 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

5. A display device comprising:

a pixel portion;

a scan line driver circuit; and

a signal line driver circuit,

wherein the pixel portion and the scan line driver circuit are formed over a substrate,

wherein the scan line driver circuit comprises a first flip-flop and a second flip-flop,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,

wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,

wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,

wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,

wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,

wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,

wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,

wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,

wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,

wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,

wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,

wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,

wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,

wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,

wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,

wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,

wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,

wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and

wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.

6. The display device according to claim 5 ,

wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

7. The display device according to claim 5 ,

wherein a first clock signal is input to the first wiring, and

wherein a second clock signal is input to the second wiring.

8. The display device according to claim 5 ,

wherein the signal line driver circuit comprises a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,

wherein the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are formed over the substrate,

wherein one of a source and a drain of the thirteenth transistor is directly connected to a third wiring,

wherein one of a source and a drain of the fourteenth transistor is directly connected to the third wiring,

wherein one of a source and a drain of the fifteenth transistor is directly connected to the third wiring,

wherein a gate of the thirteenth transistor is directly connected to a fourth wiring,

wherein a gate of the fourteenth transistor is directly connected to a fifth wiring, and

wherein a gate of the fifteenth transistor is directly connected to a sixth wiring.

9. The display device according to claim 8 ,

wherein the pixel portion comprises a plurality of source signal lines, a plurality of scan lines, and a pixel,

wherein the pixel comprises a sixteenth transistor, a first insulating film over the sixteenth transistor, a common electrode over the first insulating film, a second insulating film over the common electrode, a pixel electrode over the second insulating film, and a liquid crystal over the pixel electrode,

wherein a first source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the thirteenth transistor,

wherein a second source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fourteenth transistor,

wherein a third source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fifteenth transistor,

wherein the plurality of scan lines are electrically connected to the scan line driver circuit,

wherein one of a source and a drain of the sixteenth transistor is electrically connected to one of the plurality of source signal lines,

wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the pixel electrode, and

wherein a gate of the sixteenth transistor is electrically connected to one of the plurality of scan lines.

10. The display device according to claim 5 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

11. The display device according to claim 9 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor comprise a polycrystalline semiconductor.

12. A display panel module comprising:

a display panel; and

a circuit board,

wherein the display panel comprises:

a pixel portion;

a scan line driver circuit; and

a signal line driver circuit,

wherein the pixel portion and the scan line driver circuit are formed over a substrate,

wherein the scan line driver circuit comprises a first flip-flop and a second flip-flop,

wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,

wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,

wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,

wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,

wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,

wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,

wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,

wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,

wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,

wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,

wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,

wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,

wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,

wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,

wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,

wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,

wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,

wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,

wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,

wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,

wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,

wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,

wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring,

wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor, and

wherein the display panel and the circuit board are connected to each other by a connection wiring.

13. The display panel module according to claim 12 ,

wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

14. The display panel module according to claim 12 ,

wherein a first clock signal is input to the first wiring, and

wherein a second clock signal is input to the second wiring.

15. The display panel module according to claim 12 ,

wherein the signal line driver circuit comprises a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,

wherein the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are formed over the substrate,

wherein one of a source and a drain of the thirteenth transistor is directly connected to a third wiring,

wherein one of a source and a drain of the fourteenth transistor is directly connected to the third wiring,

wherein one of a source and a drain of the fifteenth transistor is directly connected to the third wiring,

wherein a gate of the thirteenth transistor is directly connected to a fourth wiring,

wherein a gate of the fourteenth transistor is directly connected to a fifth wiring, and

wherein a gate of the fifteenth transistor is directly connected to a sixth wiring.

16. The display panel module according to claim 15 ,

wherein the pixel portion comprises a plurality of source signal lines, a plurality of scan lines, and a pixel,

wherein the pixel comprises a sixteenth transistor, a first insulating film over the sixteenth transistor, a common electrode over the first insulating film, a second insulating film over the common electrode, a pixel electrode over the second insulating film, and a liquid crystal over the pixel electrode,

wherein a first source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the thirteenth transistor,

wherein a second source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fourteenth transistor,

wherein a third source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fifteenth transistor,

wherein the plurality of scan lines are electrically connected to the scan line driver circuit,

wherein one of a source and a drain of the sixteenth transistor is electrically connected to one of the plurality of source signal lines,

wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the pixel electrode, and

wherein a gate of the sixteenth transistor is electrically connected to one of the plurality of scan lines.

17. The display panel module according to claim 12 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

18. The display panel module according to claim 16 ,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor comprise a polycrystalline semiconductor.

19. The display panel module according to claim 12 ,

wherein the connection wiring is a flexible printed circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2016
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 038055/0967 →
Priority Claims (1)
JP 2006-269689 · Sep 29, 2006 · national
Continuity (5)
Continuation 14072878 · Nov 6, 2013
Division 13117658 · May 27, 2011
Division 12694514 · Jan 27, 2010
Division 11863913 · Sep 28, 2007
Related Publication 20160141308A1 · May 19, 2016