RRAM process with roughness tuning technology
The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.
1. A memory cell, comprising:
an insulation layer having an upper surface and an indentation in the upper surface;
an interlayer conductor in a via extending through the insulation layer in the indentation, wherein a first end of the interlayer conductor is located proximal to a bottom surface of the insulation layer and the second end of the interlayer conductor located distal to the bottom surface comprises an electrode surface recessed below the upper surface of the insulation layer;
a memory element in electrical contact with the electrode surface; and
a conductor over and in contact with the memory element within the indentation;
wherein the electrode surface has a surface roughness RA less than 3nm, and the indentation includes a concave sidewall portion above the electrode surface extending outwardly from the interlayer conductor toward the upper surface.
2. The memory cell of claim 1 , wherein the first end of the interlayer conductor is coupled to a terminal of an access device.
3. An integrated circuit comprising:
an insulation layer having an upper surface and indentations in the upper surface;
an array of memory cells, a memory cell in the array comprising;
an interlayer conductor in a via extending through the insulation layer in a corresponding indentation in the upper surface of the insulation layer; wherein a first end of the interlayer conductor is located proximal to a bottom surface of the insulation layer and the second end of the interlayer conductor located distal to the bottom surface comprises an electrode surface recessed below the upper surface of the insulation layer;
a memory element electrically coupled to the electrode surface; and
a conductor over and in contact with the memory element within the indentation;
wherein the electrode surface has a surface roughness RA less than 3nm;
wherein the indentation includes a concave sidewall portion above the electrode surface extending outwardly from the interlayer conductor toward the upper surface;
and
wherein the electrode surface is recessed below the top surface of the insulation layer; and
control circuitry to control application of bias arrangement supply voltages.
4. The memory cell of claim 1 , wherein the second end of the interlayer conductor is a smoothed surface smoothed by an ion bombardment process.
5. The memory cell of claim 1 , wherein the electrode surface is a flattened top surface of the interlayer conductor.
6. The memory cell of claim 1 , wherein the memory element is an oxide formed by a rapid thermal oxidation process of the interlayer conductor.
7. The memory cell of claim 1 , wherein the memory element essentially consists of oxides of a metal material of the interlayer conductor.
8. The memory cell of claim 1 , the memory element is characterized by having a programmable resistance.
9. The integrated circuit of claim 3 , wherein the electrode surface is a smoothed surface smoothed by an ion bombardment process.
10. The integrated circuit of claim 3 , wherein the electrode surface is a flattened top surface of the interlayer conductor.
11. The integrated circuit of claim 3 , wherein the memory element is an oxide formed by a rapid thermal oxidation process of the interlayer conductor.
12. The integrated circuit of claim 3 , wherein the memory element essentially consists of oxides of a metal material of the interlayer conductor.
13. The integrated circuit of claim 3 , the memory element is characterized by having a programmable resistance.
14. The integrated circuit of claim 3 , including an access device, and wherein the first end of the interlayer conductor is coupled to a terminal of the access device.