Arrangement and method for a power semiconductor switch

1. An arrangement for a power semiconductor switch in which a first current between a first electrode and a second electrode is configured to be controlled on the basis of a control voltage between a third electrode and the first electrode, the arrangement comprising:

an inductance connected in series with the power semiconductor switch, wherein a first end of the inductance is connected to the first electrode;

first measuring means for generating a first measurement voltage on the basis of a voltage of the first end of the inductance with respect to a reference potential, wherein the first measuring means has a first gain and a first offset;

second measuring means for generating a second measurement voltage on the basis of a voltage of a second end of the inductance with respect to the reference potential, wherein the second measuring means has a second gain that differs from the first gain and a second offset that differs from the first offset;

a comparator for comparing the first measurement voltage with the second measurement voltage; and

driver means for generating the control voltage, the driver means being configured to generate a first control voltage level and a second voltage level of the control voltage, wherein the driver means are coupled to the reference potential in such a manner that, during use, the first and second voltage levels generate different first electrode voltages with respect to the reference potential.

2. The arrangement as claimed in claim 1 , wherein the second gain is lower than the first gain and the second offset is higher than the first offset.

3. The arrangement as claimed in claim 1 , wherein the first gain, the second gain, the first offset, and the second offset are selected such that, in operation:

a change in the rate of change of the first current flowing through the inductance induces a change in a voltage difference between the first measurement voltage and the second measurement voltage; and

when the magnitude of the rate of change exceeds a set limit, the voltage difference changes polarity and the comparator changes states.

4. The arrangement as claimed in claim 3 , wherein the first gain, the second gain, the first offset, and the second offset are selected such that, in operation:

when the rate of change increases above a first limit during a turn-on event, the voltage difference reduces to zero and the comparator changes states; and

when the rate of change decreases below a second limit during a turn-off event, the voltage difference reduces to zero and the comparator changes states.

5. The arrangement as claimed in claim 1 , wherein the first gain, the second gain, the first offset and the second offset are selected such that, during the use of the arrangement, when the voltage over the inductance is zero:

the first control voltage level induces a first voltage difference level between first measurement voltage and the second measurement voltage, the first voltage difference level setting the comparator to a first state; and

the second control voltage level induces a second voltage difference level between first voltage and the second voltage, the second voltage difference level setting the comparator to a second state.

6. The arrangement as claimed in claim 1 , wherein the power semiconductor switch is a unit in which:

the first electrode includes a main terminal and an auxiliary terminal, the control voltage being supplied between the third electrode and the auxiliary terminal of the first electrode; and

the inductance is formed by a bonding wire in the unit, the voltage over the inductance being measured between the auxiliary terminal and the main terminal.

7. The arrangement as claimed in claim 1 ,

wherein the first measuring means are a first resistor averager that comprises:

a first resistor connecting the first end of the inductance to a first measurement point;

a second resistor connecting the reference potential to the first measurement point, wherein the reference potential is connected to a negative pole of a power supply for supplying the control voltage; and

a third resistor connecting an output of a voltage reference to the first measurement point, and

wherein the second measuring means are a second resistor average that comprises:

a fourth resistor connecting the second end of the inductance to a second measurement point;

a fifth resistor connecting the reference potential to the second measurement point; and

a sixth resistor connecting the output of the voltage reference to the second measurement point.

8. The arrangement as claimed in claim 1 , wherein the driver means comprises:

a power supply for supplying the control voltage between the third electrode and the first electrode, and

switching means for inverting the polarity of the control voltage supplied.

9. The arrangement as claimed in claim 8 , wherein the switching means are an H-bridge comprising:

a first branch having a series connection of two semiconductor switches between a positive pole and a negative pole of the power supply, wherein an output of the first branch is configured to drive the third electrode; and

a second branch having a series connection of two semiconductor switches between the positive pole and the negative pole, wherein an output of the second branch is configured to drive the first electrode.

10. The arrangement as claimed in claim 9 , wherein the switching means comprise a soft turn-of circuitry comprising:

a diode between the reference potential and the output of the second branch;

a series connection of a resistor and a soft turn-off semiconductor switch between the reference potential and the output of the first branch;

means for controlling the soft turn-off semiconductor switch on the basis of control signals controlling the semiconductor switches in the first and second branches, the means being configured to set the soft turn-off semiconductor switch into conductive state when the control signals set the semiconductor switches in the first and second branch into non-conductive state.

11. A method for a power semiconductor switch in which a first current between a first electrode and a second electrode is controlled on the basis of a control voltage between a third electrode and the first electrode, the power semiconductor being connected in series with an inductance, and a first end of the inductance being connected to the first electrode, the method comprising:

controlling the power semiconductor switch by generating a first control voltage level and a second voltage level of the control voltage in a manner that the first and second voltage levels generate different first electrode voltages with respect to a reference potential;

generating a first measurement voltage on the basis of a first end voltage of the inductance with respect to the reference potential by using measuring means having a first gain and a first offset;

generating a second measurement voltage on the basis of a second voltage of the inductance with respect to the reference potential by using measuring means having second gain that differs from the first gain and a second offset that differs from the first offset;

comparing the first measurement voltage with the second measurement voltage; and

generating a feedback signal on the basis of the comparison.

12. The method as claimed in claim 11 , wherein the second gain is lower than the first gain and the second offset is higher than the first offset.

13. The method as claimed in claim 11 , wherein the first gain, the second gain, the first offset, and the second offset are selected such that, during a turn-on event and a turn-off event:

a change in the rate of change of the first current flowing through the inductance induces a change in a voltage difference between first measurement voltage and the second measurement voltage, and

when the magnitude of the rate of change exceeds a limit, the voltage difference changes polarity and the comparator changes states.

14. The method as claimed in claim 11 , wherein the first gain, the second gain, the first offset and the second offset are selected such that, when the voltage over the inductance is zero:

the first control voltage level induces a first voltage difference level between first measurement voltage and the second measurement voltage, the first voltage difference level setting the comparator to a first state; and

the second control voltage level induces a second voltage difference level between first voltage and the second voltage, the second voltage difference level setting the comparator to a second state.