Flexible page sizes for virtual memory

1. A method for translating a virtual memory address into a physical memory address, comprising:

parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset;

combining the page directory entry offset with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a base address of a page table block, wherein the native page table size field indicates a size of a corresponding physical memory page;

combining the page table entry offset and the base address of the page table block to locate a page table entry, wherein the page table entry includes a base address of a physical memory page and a fragment field, wherein the size of the physical memory page is indicated by the native page table size field and a size of the fragment field is larger than the native page table size field; and

combining the access offset and the base address of the physical memory page based on the fragment field to determine the physical memory address.

2. The method according to claim 1 , wherein the native page table size enables a requested physical memory page to be accessed without requiring additional address translation, when a size of the requested physical memory page is greater than a size of the physical memory and less than a size of the virtual memory.

3. The method according to claim 1 , wherein the native page table size is used to indicate a native address space pointed to by the page table entry, based on the formula: address space=(2^ native page table size)×4 KB.

4. The method according to claim 1 , wherein a memory footprint of the page table block may be reduced when the native page table size is greater than or equal to one.

5. A processor configured to translate a virtual memory address into a physical memory address, comprising:

circuitry configured to parse the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset; and

circuitry configured to:

combine the page directory entry offset with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a base address of a page table block, wherein the native page table size field indicates a size of a corresponding physical memory page;

combine the page table entry offset and the base address of the page table block to locate a page table entry, wherein the page table entry includes a base address of a physical memory page and a fragment field, wherein the size of the physical memory page is indicated by the native page table size field and a size of the fragment field is larger than the native page table size field; and

combine the access offset and the base address of the physical memory page based on the fragment field to determine the physical memory address.

6. A non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to translate a virtual memory address into a physical memory address, the set of instructions comprising:

a parsing code segment for parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset;

a first combining code segment for combining the page directory entry offset with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field, a fragment field and a base address of a page table block, wherein the native page table size field indicates a size of a corresponding physical memory page and a size of the fragment field is larger than the native page table size field;

a second combining code segment for combining the page table entry offset and the base address of the page table block to locate a second page table entry based on the fragment field, wherein the second page table entry includes a second base address of a second physical memory page and a second fragment field, wherein the size of the second physical memory page is indicated by the native page table size field; and

a third combining code segment for combining the access offset and the second base address of the second physical memory page to determine the physical memory address.

7. The non-transitory computer-readable storage medium of claim 6 , wherein the instructions are hardware description language (HDL) instructions.

8. A method for determining a number of page table entries needed to address a given virtual address space, comprising:

determining a page size of each page table entry pointed to by a page directory entry based upon a page directory entry native page table size;

determining a page directory entry address space pointed to; and

determining the number of page table entries by dividing the page directory entry address space pointed to by the page size of each page table entry, wherein each of the page table entries includes a base address of a physical memory page and a fragment field, wherein the size of the physical memory page is indicated by a native page table size field of the page directory entry and a size of the fragment field is larger than the native page table size field.

9. The method according to claim 8 , wherein the page size of each page table entry is determined by the formula: page size=(2^ native page table size)×4 KB.

10. The method according to claim 8 , wherein the page directory address space pointed to is determined by the formula: page size of page size entry×(2^ page table block size), wherein the page table block size is a predetermined value.