Power amplifier die having multiple amplifiers
View Patent ↗An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.
1. An apparatus, comprising:
a module substrate having an upper surface and a lower surface opposing the upper surface;
a contact pad disposed over the upper surface;
a plurality of vias disposed in the module substrate, the vias being in thermal contact with the contact pad; and
an output stage comprising a second stage of a first power amplifier and a second stage of a second power amplifier, the second stage of the first power amplifier comprising a first plurality of electrical contacts, and the second stage of the second power amplifier comprising a second plurality of electrical contacts, one of the second stages being configured to be in an on-state when the other of the second stages is in an off-state, wherein each of the first and second pluralities of electrical contacts are disposed over the contact pad.
2. An apparatus as claimed in claim 1 , wherein the output stage is disposed in a single semiconductor die.
3. An apparatus as claimed in claim 2 , wherein the output stage comprises a plurality of a Group III-V semiconductor devices.
4. An apparatus as claimed in claim 3 , wherein the Group III-V semiconductor devices comprise a heterojunction bipolar transistor (HBT), or a pseudomorphic high electron mobility transistor (pHEMT).
5. An apparatus as claimed in claim 4 , wherein the first and second pluralities of electrical contacts are emitter contacts, and the single semiconductor die is flip-chip mounted over the module substrate.
6. An apparatus as claimed in claim 1 , wherein the plurality of vias is a first plurality of vias disposed in a first layer of the module substrate, and the module substrate further comprises a second layer comprising a second plurality of vias.
7. An apparatus as claimed in claim 6 , wherein the first plurality of vias is in direct contact with the contact pad; and the module substrate comprises a third layer comprising a third plurality of vias in direct contact with a base contact disposed over the lower surface of the module substrate.
8. An apparatus as claimed in claim 7 , further comprising:
a first routing layer disposed beneath and in direct contact with each of the first plurality of vias; and
a second routing layer disposed beneath and in direct contact with each of the second plurality of vias.
9. An apparatus as claimed in claim 8 , wherein the module substrate comprises at least one additional layer, comprising an additional plurality of vias.
10. An apparatus as claimed in claim 8 , wherein the first routing layer has a first width and the second routing layer has a second width, which is substantially the same as the first width.
11. An apparatus as claimed in claim 8 , wherein the first routing layer has a first width and the second routing layer has a second width, which is greater than the first width.
12. An apparatus as claimed in claim 6 , wherein each of the first and second layers of the module substrate comprises a dielectric material.
13. An apparatus as claimed in claim 6 , wherein each of the first and second layers of the module substrate comprises a ceramic material.
14. A communication device comprising the apparatus of claim 1 .
15. An apparatus, comprising:
a module substrate having an upper surface and a lower surface opposing the upper surface;
a contact pad disposed over the upper surface;
a plurality of vias disposed in the module substrate, the vias being in thermal contact with the contact pad; and
a single output stage disposed over the module substrate, and comprising: a second stage of a first power amplifier comprising a first plurality of electrical contacts, and a second stage of a second power amplifier comprising a second plurality of electrical contacts, each of the first and second pluralities of electrical contacts being interdigitated and in contact with the contact pad.
16. An apparatus as claimed in claim 15 , wherein the second stages each comprise Group III-V semiconductor devices.
17. An apparatus as claimed in claim 16 , wherein the Group III-V semiconductor devices comprise heterojunction bipolar transistors (HBTs), or pseudomorphic high electron mobility transistors (pHEMTs).
18. An apparatus as claimed in claim 17 , wherein the first and second pluralities of electrical contacts are emitter contacts, and the single output stage is flip-chip mounted over the module substrate.
19. An apparatus as claimed in claim 15 , wherein the module substrate comprises a plurality of layers, and each layer comprises a plurality of vias.
20. An apparatus as claimed in claim 19 , wherein the plurality of layers comprises:
a first layer comprising a first plurality of vias in direct contact with the contact pad; and
a second layer comprising a second plurality of vias in direct contact with a base contact disposed over the lower surface of the module substrate.
21. An apparatus as claimed in claim 20 , further comprising:
a first routing layer disposed beneath and in direct contact with each of the first plurality of vias; and
a second routing layer disposed over and in direct contact with each of the second plurality of vias.
22. An apparatus as claimed in claim 21 , wherein the plurality of layers further comprises at least one additional layer.
23. An apparatus as claimed in claim 21 , wherein the first routing layer has a first width and the second routing layer has a second width, which is substantially the same as the first width.
24. An apparatus as claimed in claim 21 , wherein the first routing layer has a first width and the second routing layer has a second width, which is greater than the first width.
25. An apparatus as claimed in claim 19 , wherein each of the plurality of layers comprises a dielectric material.
26. An apparatus as claimed in claim 19 , wherein each of the plurality of layers comprises a ceramic material.
27. A communication device comprising the apparatus as claimed in claim 15 .
28. An apparatus, comprising:
a module substrate having an upper surface and a lower surface opposing the upper surface;
a first contact pad disposed over the upper surface;
a second contact pad disposed over the upper surface;
a first plurality of vias disposed in a first layer of the module substrate, the first plurality of vias being in thermal contact with the first contact pad and the second contact pad, or both;
a single output stage comprising: a second stage of a first power amplifier comprising a first plurality of electrical contacts in contact with the first contact pad; and a second stage of a second power amplifier comprising a second plurality of electrical contacts in contact with the second contact pad;
a routing layer disposed beneath the first plurality of vias and in direct contact with the first plurality of vias; and
a second plurality of vias disposed in a second layer of the module substrate and beneath the routing layer, the second plurality of vias being in direct contact with the routing layer.
29. An apparatus as claimed in claim 28 , wherein the second stages each comprise Group III-V semiconductor devices.
30. An apparatus as claimed in claim 29 , wherein the Group III-V semiconductor devices comprise a heterojunction bipolar transistors (HBTs), or a pseudomorphic high electron mobility transistors (pHEMTs).
31. An apparatus as claimed in claim 30 , wherein the first and second pluralities of electrical contacts are emitter contacts, and the single output stage is flip-chip mounted over the module substrate.
32. An apparatus as claimed in claim 28 , wherein the routing layer is a first routing layer, and the apparatus further comprises:
a second routing layer disposed beneath and in direct contact with each of the second plurality of vias.
33. An apparatus as claimed in claim 32 , wherein the each of the first and second layers further comprises at least one additional layer, and each additional layer comprises a respective additional plurality of vias.
34. An apparatus as claimed in claim 32 , wherein the first routing layer has a first width and the second routing layer has a second width, which is substantially the same as the first width.
35. An apparatus as claimed in claim 32 , wherein the first routing layer has a first width and the second routing layer has a second width, which is greater than the first width.
36. An apparatus as claimed in claim 33 , wherein each of the first and second layers comprises a dielectric material.
37. An apparatus as claimed in claim 33 , wherein each of the first and second layers comprises a ceramic material.