PWM modulator
A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.
1. A pulse width modulation (PWM) modulator comprising:
an integrator configured to
receive a modulating signal and a square wave carrier signal,
PWM modulate the modulating signal with the square wave carrier signal, the square wave carrier signal having a frequency greater than a frequency of the modulating signal, and
output a triangular waveform;
a comparator configured to compare the triangular waveform with a fixed threshold, and output a PWM modulated square wave carrier signal;
a first circuit configured to generate an auxiliary clock signal having a phase lead with respect to a clock signal associated with the square wave carrier signal; and
a second circuit downstream from said first circuit and configured to
generate a derivative signal of the auxiliary clock signal, and
inject the derivative signal into said integrator, said second circuit comprising a logic gate.
2. The PWM modulator of claim 1 wherein said integrator comprises an operational amplifier.
3. The PWM modulator of claim 2 wherein said operational amplifier comprises a class D amplifier.
4. The PWM modulator of claim 1 wherein the triangular waveform includes a synchronous peak at vertexes thereof.
5. The PWM modulator of claim 1 wherein said integrator has a drain output configuration.
6. The PWM modulator of claim 1 wherein the square wave carrier signal has a frequency at least one order of magnitude greater than the modulating signal.
7. A pulse width modulation (PWM) modulator comprising:
an integrator configured to
receive a modulating signal and a square wave carrier signal,
PWM modulate the modulating signal with the square wave carrier signal, the square wave carrier signal having a frequency greater than a frequency of the modulating signal, and
output a triangular waveform;
a comparator configured to compare the triangular waveform with a fixed threshold, and output a PWM modulated square wave carrier signal;
a first circuit configured to generate an auxiliary clock signal having a phase lead with respect to a clock signal associated with the square wave carrier signal; and
a second circuit downstream from said first circuit and configured to
generate a derivative signal of the auxiliary clock signal, and
inject the derivative signal into said integrator, said second circuit comprising a high pass filter.
8. The PWM modulator of claim 7 wherein said integrator comprises an operational amplifier.
9. The PWM modulator of claim 8 wherein said operational amplifier comprises a class D amplifier.
10. The PWM modulator of claim 7 wherein the triangular waveform includes a synchronous peak at vertexes thereof.
11. The PWM modulator of claim 7 wherein said integrator has a drain output configuration.
12. The PWM modulator of claim 7 wherein the square wave carrier signal has a frequency at least one order of magnitude greater than the modulating signal.
13. The PWM modulator of claim 7 wherein said high pass filter comprises a capacitor and resistor coupled in series.
14. A pulse width modulation (PWM) modulator comprising:
an integrator configured to
receive a modulating signal and a square wave carrier signal,
PWM modulate the modulating signal with the square wave carrier signal, the square wave carrier signal having a frequency greater than a frequency of the modulating signal, and
output a triangular waveform including a synchronous peak at vertexes thereof;
said integrator comprising an operational amplifier;
a comparator configured to compare the triangular waveform with a fixed threshold, and output a PWM modulated square wave carrier signal;
a first circuit configured to generate an auxiliary clock signal having a phase lead with respect to a clock signal associated with the square wave carrier signal; and
a second circuit downstream from said first circuit and configured to
generate a derivative signal of the auxiliary clock signal, and
inject the derivative signal into said integrator, said second circuit comprising a capacitor and resistor coupled in series.
15. The PWM modulator of claim 14 wherein said operational amplifier comprises a class D amplifier.
16. The PWM modulator of claim 14 wherein said integrator has a drain output configuration.
17. The PWM modulator of claim 14 wherein the square wave carrier signal has a frequency at least one order of magnitude greater than the modulating signal.