Semiconductor device having asymmetrical source/drain

1. A semiconductor device, comprising:

a substrate;

active fins that protrude from the substrate and include first fin areas and recessed second fin areas;

gate stacks that cross the first fin areas;

spacers on side surfaces of the gate stacks;

a device isolation layer that covers lower portions of the active fins; and

asymmetric source/drains disposed on the second fin areas,

wherein each source/drain comprises a first crystal growth portion and a second crystal growth portion that shares a plane with the first crystal growth portion and that has a lower surface at a lower level than a lower surface of the first crystal growth portion.

2. The semiconductor device of claim 1 , further comprising:

a first residue between the first crystal growth portion and the device isolation layer; and

a second residue between the second crystal growth portion and the device isolation layer,

wherein the first residue and the second residue comprise a same material as the spacers.

3. The semiconductor device of claim 2 , wherein an upper surface of the first residue is at the same level as or a higher level than upper surfaces of the active fins, and

an upper surface of the second residue is at a lower level than the upper surface of the first residue.

4. The semiconductor device of claim 3 , wherein an upper surface of the device isolation layer that contacts the first residue and an upper surface of the device isolation layer that contacts the second residue are at the same level.

5. The semiconductor device of claim 4 , wherein a lower surface of the second crystal growth portion contacts the upper surface of the second residue and a side surface of the active fin, and a lower surface of the first crystal growth portion contacts the upper surface of the first residue and the upper surface of the active fin.

6. The semiconductor device of claim 4 , wherein each recessed second fin area comprises a recessed upper surface and a recessed side surface perpendicular to the recessed upper surface.

7. The semiconductor device of claim 6 , wherein the first crystal growth portion of the source/drain contacts the recessed upper surface and the recessed side surface of each recessed second fin area.

8. The semiconductor device of claim 1 , wherein the device isolation layer comprises a first region and a second region,

wherein the first region is disposed between the active fins,

wherein a width of the second region is greater than a width of the first region, and

wherein the second crystal growth portion overlaps the second region.

9. The semiconductor device of claim 8 , wherein the second crystal growth portion does not overlap the first region.

10. A semiconductor device, comprising:

a substrate;

active fins that protrude from the substrate; and

a source/drain that contacts at least two of the active fins at the same time and that has a merged double-diamond shape,

wherein the source/drain comprises first crystal growth portions that contact upper surfaces of the at least two of the active fins, second crystal growth portions that share at least one plane with the first crystal growth portions and that contact side surfaces of the at least two of the active fins, and a third crystal growth portion formed to merge adjacent edges of the first crystal growth portions.

11. The semiconductor device of claim 10 , wherein the second crystal growth portions contact opposite side surfaces of adjacent active fins.

12. The semiconductor device of claim 11 , wherein the third crystal growth portions are between the at least two of the active fins and vertically aligned thereto.

13. The semiconductor device of claim 10 , wherein the active fins comprises first upper surfaces contacting the source/drain, and second upper surfaces at a higher level than the first upper surfaces.

14. The semiconductor device of claim 10 , wherein lower surfaces of the first crystal growth portions are at a higher level than lower surfaces of the second crystal growth portions, and at a lower level than lower surfaces of the third crystal growth portions.

15. A semiconductor device, comprising:

a substrate;

an active fin that protrudes from the substrate; and

a diamond-shaped source/drain on an upper surface of the active fin,

wherein the diamond-shaped source/drain comprises a first crystal growth portion and a second crystal growth portion, and

wherein the second crystal growth portion comprises a lower surface that is at a lower level than a lower surface of the first crystal growth portion.

16. The semiconductor device of claim 15 , further comprising:

a device isolation layer adjacent the active fin;

a first residue between the first crystal growth portion and the device isolation layer; and

a second residue between the second crystal growth portion and the device isolation layer,

wherein an upper surface of the first residue is at a same level as or at a higher level than an upper surface of the active fin, and

wherein an upper surface of the second residue is at a lower level than the upper surface of the first residue and/or the active fin.

17. The semiconductor device of claim 16 , wherein the active fin comprises a first active fin, and wherein the diamond-shaped source/drain comprises a first diamond-shaped source/drain, the semiconductor device further comprising:

a second active fin that protrudes from the substrate and that is spaced apart from the first active fin by the device isolation layer;

a second diamond-shaped source/drain on an upper surface of the second active fin, the second diamond-shaped source/drain comprising a third crystal growth portion and a fourth crystal growth portion, wherein the fourth crystal growth portion comprises a lower surface at a lower level than a lower surface of the third crystal growth portion;

a merging crystal growth that connects the first crystal grown portion of the first diamond-shaped source/drain and the third crystal growth portion of the second diamond-shaped source/drain.

18. The semiconductor device of claim 17 ,

wherein the merging crystal growth is remote from the second crystal growth portion of the first diamond-shaped source/drain, and

wherein the merging crystal growth is remote from the fourth crystal growth portion of the second diamond-shaped source/drain.

19. The semiconductor device of claim 17 ,

wherein dopant concentration of the first diamond-shaped source/drain gradually increases towards an upper end of the first diamond-shaped source/drain.

20. The semiconductor device of claim 17 , further comprising:

a gate stack comprising a gate dielectric layer and a gate electrode;

a spacer electrically isolating the gate stack from the first diamond-shaped source/drain and the second diamond-shaped source/drain;

a contact electrode adjacent the spacer, the contact electrode in direct contact with the first diamond-shaped source/drain, the second diamond-shaped source/drain, and the merging crystal growth.