Dynamic voltage/frequency scaling for video processing using embedded complexity metrics

1. A method for dynamic voltage/frequency scaling (DVFS) for video processing, the method comprising:

parsing, at a decoder, a bitstream associated with a video to determine embedded information associated with a complexity of a first portion of the video;

estimating, at the decoder, the complexity of the first portion of the video using the embedded information, the complexity is estimated according to the following equation:

C=k init n MB +k bit n bit +k nz n nz +k intra n intra +k six n six +k α n α

where C is the estimated complexity, n MB is a number of total macroblocks in the first portion of the video, n bit is a number of bits in the first portion of the video, n nz is a number of non-zero macroblocks in the first portion of the video, n intra is a number of intra coded blocks in the first portion of the video, n six is a number of half-pel interpolation in the first portion of the video n α is a number of alpha-point deblocking in the first portion of the video, and constants k init , k bit , k nz , k intra , k six , and k α are unit complexity constants for performing macroblock initialization, one bit parsing, non-zero block transform and quantization, intra block prediction, inter-block half-pel interpolation, and deblock alpha points filtering, respectively;

determining, at the decoder, a voltage and frequency—to be used for decoding the first portion of the video based on the estimated complexity; and

decoding, at the decoder, the first portion of the video at the determined voltage and frequency.

2. The method of claim 1 , wherein the embedded information is embedded in a supplemental enhancement information (SEI) message in the bitstream.

3. The method of claim 2 , wherein the SEI message comprises a payloadType field having a value=54.

4. The method of claim 1 , wherein the embedded information is embedded in a network abstraction layer unit (NALU) header message in the bitstream.

5. The method of claim 4 , wherein the NALU header message comprises a nal_unit_type field having a value of 24.

6. The method of claim 1 , wherein the first portion of the video is a frame, a group of pictures (GOP), a scene, or a portion defined by a time interval.

7. The method of claim 1 , wherein the decoder is a high efficiency video coding (HEVC) decoder and the embedded information comprises video sequence-level parameters and parameters specific to the first portion of video.

8. The method of claim 7 , wherein the decoder comprises hardware configured to include a plurality of distinct clock domains, wherein clock frequencies of each distinct clock domain of the plurality of distinct clock domains are proportioned to achieve fine-grained voltage/frequency scaling.

9. An apparatus for dynamic voltage/frequency scaling (DVFS) for video processing, the apparatus comprising:

a video decoder configured to:

parse a bitstream associated with a video to determine embedded information associated with a complexity of a first portion of the video;

estimate the complexity of the first portion of the video using the embedded information, the complexity is estimated according to the following equation:

C=k init n MB +k bit n bit +k nz n nz +k intra n intra +k six n six +k α n α

where C is the estimated complexity, n MB is a number of total macroblocks in the first portion of the video, n bit is a number of bits in the first portion of the video, n nz is a number of non-zero macroblocks in the first portion of the video, n intra is a number of intra coded blocks in the first portion of the video, n six is a number of half-pel interpolation in the first portion of the video, n α is a number of alpha-point deblocking in the first portion of the video, and constants k init , k bit , k nz , k intra , k six , and k α are unit complexity constants for performing macroblock initialization, one bit parsing, non-zero block transform and quantization, intra block prediction, inter-block half-pel interpolation, and deblock alpha points filtering, respectively;

determine a voltage to be used for decoding the first portion of the video based on the estimated complexity; and

decode the first portion of the video at the determined voltage and frequency.

10. The apparatus of claim 9 , wherein the embedded information is embedded in a supplemental enhancement information (SEI) message in the bitstream.

11. The apparatus of claim 10 , wherein the SEI message comprises a payloadType field having a value=54.

12. The apparatus of claim 9 , wherein the embedded information is embedded in a network abstraction layer unit (NALU) header message in the bitstream.

13. The apparatus of claim 12 , wherein the NALU header message comprises a nal_unit_type field having a value of 24.

14. The apparatus of claim 9 , wherein the first portion of the video is a frame, a group of pictures (GOP), a scene, or a portion defined by a time interval.

15. The apparatus of claim 9 , wherein the video decoder is a high efficiency video coding (HEVC) decoder and the embedded information comprises video sequence-level parameters and parameters specific to the first portion of video.

16. The apparatus of claim 9 , wherein the decoder comprises hardware configured to include a plurality of distinct clock domains, wherein clock frequencies of each distinct clock domain of the plurality of distinct clock domains are proportioned to achieve fine-grained voltage/frequency scaling.

17. A method for buffer-assisted dynamic voltage/frequency scaling (DVFS) for video processing, the method comprising:

determining, at a video receiver, a first clock frequency to be used for decoding a first portion of a video based on an estimated complexity of the first portion of the video, the complexity is estimated according to the following equation:

C=k init n MB +k bit n bit +k nz n nz +k intra n intra +k six n six +k α n α

where C is the estimated complexity, n MB is a number of total macroblocks in the first portion of the video, n bit is a number of bits in the first portion of the video, n nz is a number of non-zero macroblocks in the first portion of the video, n intra is a number of intra coded blocks in the first portion of the video, n six is a number of half-pel interpolation in the first portion of the video, n α is a number of alpha-point deblocking in the first portion of the video, and constants k init , k bit , k nz , k intra , k six , and k α are unit complexity constants for performing macroblock initialization, one bit parsing, non-zero block transform and quantization, intra block prediction, inter-block half-pel interpolation, and deblock alpha points filtering, respectively;

decoding, at the video receiver, the first portion of the video at the first clock frequency;

loading, by the video receiver, the first portion of the video into a frame buffer until the frame buffer reaches a high threshold;

displaying, at the video receiver, some of the first portion of the video stored in the frame buffer until the frame buffer reaches a low threshold;

changing, at the video receiver, to a second clock frequency; and

decoding, at the video receiver, a second portion of the video at the second clock frequency and loading the second portion of the video into the frame buffer.

18. The method of claim 17 , wherein the first clock frequency is determined according to the following equation:

f

init

=

N

H

·

C

ave

t

init

where f init is the first clock frequency, N H is a number of frames associated with the high threshold of the frame buffer, C ave is the estimated complexity of the first portion of the video, and t init is an initial delay time associated with loading the frame buffer to the high threshold.

19. The method of claim 17 , wherein the second clock frequency is determined according to the following equation:

f

=

N

H

·

C

ave

t

L

,

t

L

=

B

L

a

·

w

·

h

where f is the second clock frequency, N H is a number of frames associated with the high threshold of the frame buffer, C ave is an estimated complexity of the second portion of the video, B L is an occupied memory size of the frame buffer at a low watermark th L , a is a video color format scaling factor, and w and h are a width and height of the video.

20. The method of claim 17 , further comprising:

parsing, at the video receiver, a bitstream associated with the video to determine embedded information associated with the estimated complexity of the first portion of the video; and

determining, at the video receiver, the estimated complexity of the first portion of the video using the embedded information.