Gate driver integrated on display panel
Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.
1. A gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines, wherein a stage comprises:
a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to an output terminal of a present stage and an input terminal connected to a first clock terminal;
a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node; and
a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to an input terminal which is directly connected to the first node of the present stage, and an output terminal connected to the buffer node.
2. The gate driver of claim 1 , the stage further comprises:
a first node pull-up portion having a seventh transistor and a eighth transistor serially connected, wherein the seventh transistor having an input terminal connected to a first DC voltage input terminal, an output terminal connected to an input terminal of the eighth transistor and a control terminal connected to an output terminal of a previous stage, and wherein the eighth transistor having an input terminal connected to the output terminal of the seventh transistor, an output terminal connected to the first node and a control terminal connected to a first node of the previous stage.
3. The gate driver of claim 2 , the stage further comprises:
a first node reset portion having a ninth transistor and a tenth transistor serially connected, wherein the ninth transistor having an input terminal connected to a second DC voltage input terminal, an output terminal connected to an input terminal of the tenth transistor and a control terminal connected to an output terminal of a subsequent stage, and wherein the tenth transistor having an input terminal connected to the output terminal of the ninth transistor, an output terminal connected to the first node of the present stage and a control terminal connected to a first node of the subsequent stage.
4. The gate driver of claim 1 , the stage further comprises:
a first node reset portion having a ninth transistor and a tenth transistor serially connected, wherein the ninth transistor having an input terminal connected to a second DC voltage input terminal, an output terminal connected to an input terminal of the tenth transistor and a control terminal connected to an output terminal of a subsequent stage, and wherein the tenth transistor having an input terminal connected to the output terminal of the ninth transistor, an output terminal connected to the first node and a control terminal connected to a first node of the subsequent stage.
5. A gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines, wherein a stage comprises:
a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to an output terminal of a present stage and an input terminal connected to a first clock terminal;
a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node; and
a first node reset portion having a third transistor and a fourth transistor serially connected, wherein the third transistor having an input terminal connected to a second DC voltage input terminal, an output terminal connected to an input terminal of the fourth transistor and a control terminal connected to an output terminal of a subsequent stage, and wherein the fourth transistor having an input terminal connected to an output terminal of the third transistor, an output terminal connected to the first node and a control terminal directly connected to a first node of the subsequent stage.
6. A gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines, wherein a stage comprises:
a pull-up driver including a first transistor and a capacitor, the first transistor having a control terminal connected to a first node, an output terminal connected to an output terminal of a present stage and an input terminal connected to a first clock terminal, the capacitor being connected between the first node and the output terminal of the present stage;
a first node pull-down portion including a second transistor and a third transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, the third transistor having an input terminal connected to a buffer node, an output terminal connected to a low voltage input terminal and a control terminal connected to a second node;
a buffer node stabilizer including a fourth transistor, the fourth transistor having an input terminal and a control terminal connected to an input terminal which is directly connected to the first node of the present stage, and an output terminal connected to the buffer node;
an output pull-down portion having a fifth transistor, the fifth transistor having an input terminal connected to the output terminal of the stage, an output terminal connected to the low voltage input terminal and a control terminal connected to a second clock terminal having an opposite phase to the first clock terminal;
a reset portion including a sixth transistor, the sixth transistor having an input terminal connected to the second node, an output terminal connected to the low voltage input terminal and a control terminal connected to the first node;
a first node pull-up portion having a seventh transistor and a eighth transistor serially connected, wherein the seventh transistor having an input terminal connected to a first DC voltage input terminal, an output terminal connected to an input terminal of the eighth transistor and a control terminal connected to an output terminal of a previous stage, and wherein the eighth transistor having an input terminal connected to the output terminal of the seventh transistor, an output terminal connected to the first node and a control terminal connected to a first node of the previous stage; and
a first node reset portion having a ninth transistor and a tenth transistor serially connected, wherein the ninth transistor having an input terminal connected to a second DC voltage input terminal, an output terminal connected to an input terminal of the tenth transistor and a control terminal connected to an output terminal of a subsequent stage, and wherein the tenth transistor having an input terminal connected to the output terminal of the ninth transistor, an output terminal connected to the first node of the present stage and a control terminal directly connected to a first node of the subsequent stage.