Semiconductor apparatus including multichip package
A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. The slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage.
1. A multichip package comprising:
a master chip mounted on a substrate, configured to receive an external signal through the substrate, and including a master region and a slave region;
a plurality of slave chips stacked on the master chip, each of the slave chips including a required driving region and a non-required driving region; and
a voltage providing unit configured to provide voltages to the master region and the slave region of the master chip and the required driving regions and the non-required driving regions,
wherein the voltage providing unit is configured to provide a first internal voltage to the master region of the master chip and a second internal voltage having the same level as the first internal voltage to the slave region of the master chip, and provide the first internal voltage to the required driving regions and the second internal voltage smaller than the first internal voltage to the non-required driving regions.
2. The multichip package of claim 1 , wherein the master chip and the plurality of slave chips are configured to be electrically coupled to each other through a through silicon via (TSV).
3. The multichip package of claim 1 , wherein the voltage providing unit is located in any one of the plurality of slave chips selected from among the plurality of slave chips.
4. The multichip package of claim 1 , wherein the plurality of slave chips have the same structure as the master chip, and
the required driving region is a slave region, and the non-required driving region is a master region.
5. The multichip package of claim 1 , wherein the voltage providing unit includes:
a first bulk voltage generator configured to generate an operation bulk voltage;
a second bulk voltage generator configured to generate a standby bulk voltage having a lower level than the operation bulk voltage;
a selection unit configured to receive the operation bulk voltage and the standby bulk voltage, and selectively output the operation bulk voltage and the standby bulk voltage as the first internal voltage and the second internal voltage; and
a setting circuit unit configured to generate a control signal of the selection unit according to a signal for setting a chip to which the first internal voltage and the second internal voltage are output.
6. The multichip package of claim 5 , wherein the selection unit is configured to output the operation bulk voltage as the first and second internal voltages when the first and second internal voltages are provided to the master chip.
7. The multichip package of claim 6 , wherein the selection unit is configured to output the operation bulk voltage as the first internal voltage and the standby bulk voltage as the second internal voltage when the first and second internal voltages are provided to any one of the slave chips.
8. The multichip package of claim 1 , wherein any one of the master chip and the plurality of slave chips further includes a mode register set (MRS) circuit unit, and
the setting circuit unit is configured to receive a signal for setting a chip to which the first and second internal voltages are output from the MRS circuit unit.
9. The multichip package of claim 5 , wherein the operation bulk voltage is a ground voltage (VSS), and the standby bulk voltage is a negative voltage (VBB).