Management of data storage in memory cells using a non-integer number of bits per cell
A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.
1. An apparatus for data storage, comprising:
a memory including an array of memory cells; and
storage circuitry configured to:
determine, for a group of the memory cells, a cell occupancy level for each of a number of programming states, wherein the cell occupancy level corresponds to an expected number of the memory cells in the group that are to be programmed to each programming state of the number of programming states;
set a respective threshold voltage for each programming state based on the respective cell occupancy level and a cell occupancy level of at least one adjacent programming state; and
program each memory cell in the group of the memory cells using a corresponding threshold voltage.
2. The apparatus according to claim 1 , wherein the storage circuitry is further configured to program each memory cell in the group to one of a subset of the number of programming states in a first programming operation.
3. The apparatus of claim 2 , wherein the storage circuitry is further configured to program a portion of the memory cells to at least one programming state that is excluded from the subset of the number of programming states, wherein the portion of the memory cells are selected from memory cells programmed to a portion of the subset of the number of programming states.
4. The apparatus of claim 1 , wherein a voltage difference between a first threshold voltage and a next lower threshold voltage is different than a voltage difference between the first threshold voltage and a next higher third threshold voltage.
5. The apparatus of claim 1 , wherein to set the respective threshold voltage for each programming state, the storage circuitry is further configured to determine a number of read operations performed on the group of the memory cells.
6. The apparatus of claim 1 , wherein each memory cell in the group of the memory cells includes a non-volatile memory cell.
7. A method for data storage, comprising:
for a group of memory cells, determining a cell occupancy level for each of a number of programming states, wherein the cell occupancy level corresponds to an expected number of memory cells in the group of memory cells that are to be programmed to each programming state of the number of programming states;
setting a respective threshold voltage for each programming state based on the respective cell occupancy level and a cell occupancy level of at least one adjacent programming state; and
programming each memory cell in the group of memory cells using a corresponding threshold voltage.
8. The method of claim 7 , further comprising programming each memory cell in the group of memory cells to one of a subset of the number of programming states in a first programming operation.
9. The method of claim 8 , further comprising programming a portion of memory cells in the group of memory cells to at least one programming state that is excluded from the subset of the number of programming states, wherein the portion of memory cells are selected from memory cells programmed to a portion of the subset of the number of programming states.
10. The method according to claim 7 , wherein the cell occupancy level for each of the number of programming states is non-uniform.
11. The method of claim 7 , wherein a voltage difference between a first threshold voltage and a next lower threshold voltage is different than a voltage difference between the first threshold voltage and a next higher threshold voltage.
12. The method of claim 7 , wherein setting the respective threshold voltage for each programming state includes determining a number of read operations performed on the group of memory cells.
13. The method of claim 7 , wherein each memory cell in the group of memory cells includes a non-volatile memory cell.
14. A system, comprising:
a host;
a memory device including a plurality of memory cells; and
a memory controller configured to:
determine, for a subset of the plurality of memory cells, a cell occupancy level for each of a number of programming states, wherein the cell occupancy level corresponds to an expected number of the memory cells in the subset that are to be programmed to each programming state of the number of programming states;
set a respective threshold voltage for each programming state based on the respective cell occupancy level and a cell occupancy level of at least one adjacent programming state, wherein a voltage difference between a first threshold voltage and a next lower threshold voltage is different than a voltage difference between the first threshold voltage and a next higher threshold voltage; and
program each memory cell in the subset of the plurality of memory cells using a corresponding threshold voltage.
15. The system of claim 14 , wherein the memory controller is further configured to program each memory cell in the subset of the plurality of memory cells to one of a subset of the number of programming states in a first programming operation.
16. The system of claim 15 , wherein the memory controller is further configured to program a portion of the memory cells in the subset of the plurality of memory cells to at least one programming state that is excluded from the subset of the number of programming states, wherein the portion of the memory cells are selected from memory cells programmed to a portion of the subset of the number of programming states.
17. The system of claim 14 , wherein the cell occupancy level for each of the number of programming states is non-uniform.
18. The system of claim 14 , wherein to set the respective threshold voltage for each programming state, the memory controller is further configured to determine a number of read operations performed on the subset of the plurality of memory cells.
19. The system of claim 14 , wherein the program each memory cell in the subset, the memory controller is further configured to encode data to be stored in each memory cell in the subset with an Error Correction Code (ECC).
20. The system of claim 14 , wherein each memory cell in the plurality of memory cells includes a non-volatile memory cell.