PFC signal generation circuit, PFC control system using the same, and PFC control method
A PFC signal generation circuit which generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch includes: a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor; a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing, when a zero current detection timing of the second inductor is earlier than the target timing, and to turn on the second switch at a target timing in a subsequent cycle, when it is later than an allowable period from the target timing; and a second control signal output circuit that generates a second PFC signal to turn on the second switch according to a control signal.
1. A PFC signal generation circuit that generates a PFC signal to control a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch, the PFC signal generation circuit comprising:
a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor;
a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing in a first cycle, when a zero current detection timing of the second inductor is earlier than the target timing in the first cycle, and to turn on the second switch at a target timing in a second cycle, which is subsequent to the first cycle, when the zero current detection timing of the second inductor is later than an allowable period in the first cycle from the target timing in the first cycle; and
a second control signal output circuit that generates a second PFC signal to turn on the second switch, according to the control signal,
wherein when the zero current detection timing of the second inductor is within the allowable period in the first cycle, the timing adjustment circuit generates, at the zero current detection timing of the second inductor, the control signal to turn on the second switch,
wherein the target timing in the first cycle occur at a first redetermined time from the beginning of the first cycle, the target timing in the second cycle occur at a second predetermined time from the beginning of the second cycle, and the allowable period in the first cycle occur at a third predetermined time from the target timing in the first cycle.
2. The PFC signal generation circuit according to claim 1 , further comprising a first counter having a count value cleared at the zero current detection timing of the first inductor.
3. The PFC signal generation circuit according to claim 2 , further comprising a counter clear control circuit that clears the count value after waiting until a cycle lower limit is reached, when the zero current detection timing of the first inductor is below the cycle lower limit.
4. The PFC signal generation circuit according to claim 2 , further comprising a capture circuit that acquires a maximum count value of the first counter in a preceding cycle,
wherein the target timing is determined based on the maximum count value.
5. The PFC signal generation circuit according to claim 4 , further comprising:
a shift circuit that generates a set value of the target timing from the maximum count value; and
a first digital comparator that compares the set value of the target timing with the count value of the first counter, and generates the target timing.
6. The PFC signal generation circuit according to claim 4 , wherein the target timing is in a range from ⅜ to ⅝ of the maximum count value.
7. The PFC signal generation circuit according to claim 4 , wherein the allowable period is in a range from 1/64 to ⅛ of the maximum count value.
8. The PFC signal generation circuit according to claim 2 , further comprising a second counter that counts down a set value of a pulse width of the second PFC signal determined based on a feedback signal from the PFC circuit.
9. The PFC signal generation circuit according to claim 8 , further comprising a second digital comparator that compares the count value of the first counter with a set value of a pulse width of the first PFC signal determined based on the feedback signal.
10. A PFC control system comprising:
a PFC circuit connected to an AC power supply; and
a PFC signal generation circuit that generates a PFC signal to control the PFC circuit, wherein
the PFC circuit comprises:
a first inductor connected to a first switch; and
a second inductor connected to a second switch, and
the PFC signal generation circuit comprises:
a first control signal output circuit that outputs a first PFC signal to turn on the first switch at a zero current detection timing of the first inductor;
a timing adjustment circuit that generates a control signal to turn on the second switch after waiting until a target timing in a first cycle, when a zero current detection timing of the second inductor is earlier than the target timing in the first cycle, and to turn on the second switch at a target timing in a second cycle, which is subsequent to the first cycle, when the zero current detection timing of the second inductor is later than an allowable period in the first cycle from the target timing in the first cycle; and
a second control signal output circuit that generates a second PFC signal to turn on the second switch, according to the control signal,
wherein when the zero current detection timing of the second inductor is within the allowable period in the first cycle, the timing adjustment circuit generates, at the zero current detection timing of the second inductor, the control signal to turn on the second switch,
wherein the target timing in the first cycle occur at a first predetermined time from the beginning of the first cycle, the target timing in the second cycle occur at a second predetermined time from the beginning of the second cycle, and the allowable period in the first cycle occur at a third predetermined time from the target timing in the first cycle.
11. The PFC control system according to claim 10 , wherein the PFC circuit further comprises a counter having a count value cleared at the zero current detection timing of the first inductor.
12. The PFC control system according to claim 11 , further comprising a counter clear control circuit that clears the count value after waiting until a cycle lower limit is reached, when the zero current detection timing of the first inductor is below the cycle lower limit.
13. The PFC control system according to claim 11 , wherein
the PFC circuit further comprises a capture circuit that acquires a maximum count value of the counter in a preceding cycle, and
the target timing is determined based on the maximum count value.
14. The PFC control system according to claim 13 , further comprising:
a shift circuit that generates a set value of the target timing from the maximum count value; and
a first digital comparator that compares the set value of the target timing with the count value of the counter, and generates the target timing.
15. The PFC control system according to claim 10 , further comprising an arithmetic circuit that determines a pulse width of each of the first and second PFC signals based on a feedback signal from the PFC circuit.
16. The PFC control system according to claim 10 , further comprising a DC/DC converter supplied with an output voltage of the PFC circuit.
17. The PFC control system according to claim 16 , further comprising a light-emitting diode supplied with an output voltage of the DC/DC converter.
18. A PFC control method that controls a PFC circuit including a first inductor connected to a first switch and a second inductor connected to a second switch, the PFC control method comprising:
turning on the first switch at a zero current detection timing of the first inductor;
turning on the second switch after waiting until a target timing in a first cycle, when a zero current detection timing of the second inductor is earlier than the target timing in the first cycle; and
turning on the second switch at a target timing in a second cycle, which is subsequent to the first cycle, when the zero current detection timing of the second inductor is later than an allowable period in the first cycle from the target timing in the first cycle,
wherein when the zero current detection timing of the second inductor is within the allowable period in the first cycle, the second switch is turned on at the zero current detection timing of the second inductor,
wherein the target timing in the first cycle occur at a first predetermined time from the beginning of the first cycle, the target timing in the second cycle occur at a second predetermined time from the beginning of the second cycle, and the allowable, period in the first cycle occur at a third predetermined time from the target timing in the first cycle.