Encryption interface
Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.
1. A processor comprising:
a system agent to communicate a plaintext request with a hardware functional block;
a tweak buffer to store a tweak until the plaintext request is received at an encryption interface, wherein the tweak is a unique address indicating a location of data for the plaintext request in a main memory;
the encryption interface coupled between an upstream component and a downstream component the encryption interface being transparent to at least one of the upstream component or the downstream component, wherein the encryption interface is to:
receive the plaintext request from the upstream component;
encrypt the plaintext request to obtain an encrypted request, wherein the encryption interface is to emulate the upstream component interfacing with the component by structuring the encrypted request to be a same structure as messages sent directly from the upstream component to the downstream component; and
communicate the encrypted request to downstream component; and
the downstream component to communicate the encrypted request to the main memory of a computing device.
2. The processor of claim 1 , wherein the encryption interface and the upstream component are integrated into a system on a chip (SoC).
3. The processor of claim 1 , wherein the encryption interface to encrypt the plaintext request using an advanced encryption standard (AES) xor-encrypt-xor (XEX) encryption mode with tweak and ciphertext stealing (XTS) encryption.
4. The processor of claim 3 , wherein the encryption interface to use the AES XTS encryption to generate the tweak, wherein the tweak is a unique address indicating a location of data for the plaintext request in the main memory.
5. The processor of claim 1 , wherein the encryption interface is further to:
receive a plurality of request messages at the encryption interface;
buffer the plurality of request messages at a request buffer of the encryption interface; and
select the request message from the plurality of request messages at the request buffer to communicate to the downstream component.
6. The processor of claim 5 , wherein the encryption interface is further to bypass the request buffer to send the request message directly to the downstream component when the request buffer is empty.
7. The processor of claim 1 , wherein the plaintext request is a first request to read data from the main memory or a second request to write data to the main memory.
8. The processor of claim 1 , wherein the hardware functional block is at least one of a processor core, a graphics core, a cache agent, a second upstream component, or a memory agent.
9. A method comprising:
receiving, at an encryption interface, an encrypted response from a downstream component;
decrypting, by the encryption interface, the encrypted response to obtain a decrypted response, wherein the encryption interface emulates the downstream component interfacing with a upstream component by structuring the encrypted request to be a same structure as messages sent directly from the upstream component to the downstream component; and
sending, from the encryption interface, the decrypted response to the upstream component wherein the system agent upstream component communicates the decrypted response to an application.
10. The method of claim 9 , further comprising:
storing, at a ciphertext buffer, the encrypted response while the encryption interface computes a tweak for an encrypted request, wherein the ciphertext buffer stores a plurality of encrypted responses; and
selecting, by the encryption interface, the encrypted response from the plurality of encrypted responses to decrypt.
11. The method of claim 10 , further comprising decrypting the encrypted response using a decryption engine to obtain the decrypted response, wherein the decryption engine uses an advanced encryption standard (AES) xor-encrypt-xor (XEX) encryption mode with tweak and ciphertext stealing (XTS) encryption standard to decrypt the encrypted response.
12. The method of claim 11 , further comprising bypassing the ciphertext buffer to send the encrypted response directly to the decryption engine when the ciphertext buffer is empty.
13. The method of claim 9 , further comprising selecting a response link to send the decrypted response to the upstream component while the encrypted response is decrypted.
14. The processor of claim 1 , wherein the upstream component is the system agent is and the downstream component is a memory controller.
15. The method of claim 9 , wherein the upstream component is a system agent is and the downstream component is a memory controller.