Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermetically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.
1. A method of packaging a microelectronic device, the method comprising:
hermetically sealing a first sensor within a first cavity by affixing a first sensor chip to a first side of an interposer;
hermetically sealing a second sensor within a second cavity by affixing a second sensor chip to the first side of the interposer; and
electrically coupling an integrated circuit (IC) chip to the first sensor by affixing the IC chip to a second side of the interposer, opposite the first sensor chip, the interposer including a through via electrically connecting the first and second sides of the interposer, wherein the first sensor comprises a first micro-electro-mechanical system including a mechanically displaceable structure anchored to the first sensor chip.
2. The method of claim 1 , wherein affixing a first sensor chip to the first side of the interposer and affixing a second sensor chip to the interposer further comprises:
simultaneously applying a pressure to both the first and second sensor chips against the interposer, and
heating the interposer to permanently affix the first and second sensor chips.
3. The method of claim 1 , wherein affixing the IC chip to a second side of the interposer further comprises solder bonding the IC chip after affixing the first and second sensor chips to the interposer.
4. The method of claim 3 , wherein affixing the first and second sensor chips to the interposer further comprises joining bond pads of the interposer to bond pads of the first and second sensor chips with a first solder joint at a first soldering temperature; and wherein affixing the IC chip to the interposer further comprises joining bond pads of the interposer to bond pads of the IC chip with a second solder joint at a second soldering temperature which does not cause the first solder joint to reflow.
5. The method of claim 4 , wherein joining bond pads of the interposer to bond pads of the first and second sensor chips with the first solder joint further comprises forming the first solder joint with a high temperature solder composition; and
wherein joining bond pads of the interposer to bond pads of the IC chip with the second solder joint further comprises forming the second solder joint with a low temperature solder composition.
6. The method of claim 4 , wherein joining bond pads of the interposer to bond pads of the first and second sensor chips with the first solder joint further comprises forming the first solder joint with a low temperature solder composition and annealing the first solder joint to form a intermetallic compound having a higher melting temperature than the first soldering temperature; and
wherein joining bond pads of the interposer to bond pads of the IC chip with the second solder joint further comprises forming the second solder joint with a low temperature solder composition.
7. The method of claim 1 , further comprising:
forming lateral electrical interconnect traces across at least one of the first and second sides of the interposer to electrically couple a first interposer bond pad affixed to at least one of: the IC chip, the first sensor chip, and the second sensor chip to a second interposer bond pad to be affixed to a printed circuit board (PCB).
8. The method of claim 7 , wherein forming lateral electrical interconnect traces further comprises an anisotropic conductive adhesive (ACA) process including printing or lamination of the ACA or further comprises a semiconductor wafer interconnect process sequence including dielectric film deposition, dielectric film etching, and metal trace plating.