Class AB inverting driver for PNP bipolar transistor LDO regulator
A driver circuit for a PNP power transistor in an LDO regulator uses a Class AB (push-pull) buffer to supply the necessary base current to an NPN driver transistor, where the NPN driver transistor has its collector connected to the base of the PNP power transistor. A front end circuit of the driver, coupled to drive the Class AB buffer, uses a current diverting transistor, where a first portion of the current is used to control the pull-up transistor in the Class AB buffer, and the remainder of the current is used to control the pull-down transistor in the Class AB buffer, so the driver is very efficient. The portion of the driver circuit between the input of the driver circuit and the base of the NPN driver transistor is an inverting circuit. The driver can properly operate with an input voltage within two diode drops of ground.
1. A low dropout (LDO) regulator comprising:
a first PNP transistor connected in series between an input voltage Vin terminal and an output voltage Vout terminal for coupling to a load;
an NPN driver transistor having a collector coupled to a base of the first PNP transistor, for controlling a conductivity of the PNP transistor, and having an emitter coupled to ground;
an error amplifier receiving a voltage corresponding to the output voltage and receiving a set voltage, the error amplifier being connected in a feedback loop for matching the voltage corresponding to the output voltage to the set voltage; and
an inverting circuit comprising:
a push-pull circuit connected to a base of the NPN driver transistor, the push-pull circuit comprising a second PNP transistor, acting as a pull-up transistor, and a first NPN transistor, acting as a pull-down transistor;
a first control circuit connected to a base of the second PNP transistor;
a second control circuit connected to a base of the first NPN transistor; and
a current diverting transistor, coupled to a first current source, controlling an amount of current to the first control circuit and to the second control circuit, wherein a base of the current diverting transistor is coupled to an output of the error amplifier,
wherein the inverting circuit is connected between the input voltage and ground, and wherein the inverting circuit has a minimum voltage drop between the input voltage and ground less than two diode drops to allow the inverting circuit to operate with an input voltage within two diode drops above ground.
2. The regulator of claim 1 wherein the current diverting transistor comprises a second NPN transistor having a collector coupled to the first current source,
wherein the first control circuit is coupled to the collector of the second NPN transistor, and
wherein the second control circuit is coupled to an emitter of the second NPN transistor.
3. The regulator of claim 2 wherein the first control circuit comprises a current mirror having an input coupled to the collector of the second NPN transistor,
wherein an output of the current mirror is coupled to a base of a third NPN transistor acting as a pull-up transistor for the second PNP transistor.
4. The regulator of claim 3 wherein the second control circuit comprises a third PNP transistor having a base coupled to the emitter of the second NPN transistor,
wherein the third PNP transistor acts as a pull-down transistor for the first NPN transistor.
5. The regulator of claim 1 further comprising a first capacitor and first resistor coupled between the error amplifier and the base of the current diverting transistor to increase the LDO regulator bandwidth by compensating for the pole at the base of the first PNP transistor, thereby also improving high frequency PSRR performance.
6. The regulator of claim 5 further comprising a second capacitor and second resistor coupled between the base of the current diverting transistor and the base of the NPN driver transistor.
7. The regulator of claim 1 further comprising a capacitor and resistor coupled between the base of the current diverting transistor and the base of the NPN driver transistor.
8. The regulator of claim 1 wherein the set voltage equals a target Vout level.
9. The regulator of claim 1 wherein the set voltage equals a divided Vout when Vout is at a target voltage.