Circuit modification
Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.
1. A system for modifying a circuit comprising:
a processor to:
generate a set of testing data, the set of testing data comprising at least a first virtual memory address corresponding to a first set of tables and a first physical memory address, and a second virtual memory address corresponding to a second set of tables and a second physical memory address;
detect a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change the first physical memory address associated with the first virtual memory address to the second physical memory address;
generate a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path;
transmit the test template to the circuit for each of a plurality of software instruction threads;
detect a defect in the execution of the test template by the circuit; and
modify the circuit to prevent the defect during execution of the test template.
2. The system of claim 1 , wherein the processor is to modify properties of the translation path, the properties comprising a page size or a caching property.
3. The system of claim 1 , wherein the translation path comprises a mapping from a range of virtual memory addresses to a range of physical memory addresses.
4. The system of claim 3 , wherein the mapping from the range of virtual memory addresses to the range of physical memory addresses corresponds to a translation look aside buffer.
5. The system of claim 1 , wherein the processor is to:
detect a result from the execution of the second instruction; and
determine that the result corresponds to an unexpected value that differs from a value stored at the second physical memory address.
6. The system of claim 1 , wherein the processor is to store the first instruction, the second instruction, the translation path, and the set of testing data in a database.
7. The system of claim 1 , wherein the processor is to generate the predetermined modification based on constraints associated with the translation path.
8. The system of claim 1 , wherein the first instruction is an atomic instruction comprising a semaphore.
9. A method for modifying a circuit comprising:
generating a set of testing data, the set of testing data comprising at least a first virtual memory address corresponding to a first set of tables and a first physical memory address, and a second virtual memory address corresponding to a second set of tables and a second physical memory address;
detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change the first physical memory address associated with the first virtual memory address to the second physical memory address;
generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path;
transmitting the test template to the circuit for each of a plurality of software instruction threads;
detecting a defect in the execution of the test template by the circuit; and
modifying the circuit to prevent the defect during execution of the test template.
10. The method of claim 9 , comprising modifying properties of the translation path, the properties comprising a page size or a caching property.
11. The method of claim 9 , wherein the translation path comprises a mapping from a range of virtual memory addresses to a range of physical memory addresses.
12. The method of claim 11 , wherein the mapping from the range of virtual memory addresses to the range of physical memory addresses corresponds to a translation look aside buffer.
13. The method of claim 9 , wherein detecting the defect comprises:
detecting a result from the execution of the second instruction; and
determining that the result corresponds to an unexpected value that differs from a value stored at the second physical memory address.
14. The method of claim 9 , comprising generating the predetermined modification based on constraints associated with the translation path.
15. A computer program product for modifying a circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to:
generate a set of testing data, the set of testing data comprising at least a first virtual memory address corresponding to a first set of tables and a first physical memory address, and a second virtual memory address corresponding to a second set of tables and a second physical memory address;
detect a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change the first physical memory address associated with the first physical memory address to the second physical memory address;
generate a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path;
transmit the test template to the circuit for each of a plurality of software instruction threads;
detect a defect in the execution of the test template by the circuit; and
modify the circuit to prevent the defect during execution of the test template.
16. The computer program product of claim 15 , wherein the program instructions cause the processor to modify properties of the translation path, the properties comprising a page size or a caching property.
17. The computer program product of claim 15 , wherein the program instructions cause the processor to map from a range of virtual memory addresses to a range of physical memory addresses.
18. The computer program product of claim 17 , wherein the mapping from the range of virtual memory addresses to the range of physical memory addresses corresponds to a translation look aside buffer.
19. The computer program product of claim 15 , wherein the program instructions cause the processor to:
detect a result from the execution of the second instruction; and
determine that the result corresponds to an unexpected value that differs from a value stored at the second physical memory address.
20. The computer program product of claim 15 , wherein the program instructions cause the processor to generate the predetermined modification based on constraints associated with the translation path.