Semiconductor memory device having inverting circuit and controlling method there of
A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
1. A method of controlling a memory, the method comprising:
receiving a control signal at a control terminal;
receiving an input data to be written to a plurality of memory banks via data terminals;
performing an inverting mode for inverting or non-inverting the input data, using an inverting circuit, based on the control signal according to a first mode register signal; and
performing a data masking mode for masking the input data, using a data masking circuit, based on the control signal according to a second mode register signal,
wherein the inverting circuit is disposed for each of the plurality of memory banks.
2. The method of claim 1 , wherein performing the inverting mode includes generating an inversion control signal, using a control signal generating circuit, in response to the control signal and the first mode register signal.
3. The method of claim 2 , further comprising:
providing an enable signal as the inversion control signal to the inverting circuit to invert the input data; or
providing a disable signal as the inversion control signal to the inverting circuit to prevent the input data from being inverted.
4. The method of claim 2 , wherein the control signal generating circuit is disposed for each of the plurality of memory banks.
5. The method of claim 1 , performing the data masking mode includes generating a mask control signal, using a control signal generating circuit, in response to the control signal and the second mode register signal.
6. The method of claim 5 , further comprising:
providing an enable signal as the mask control signal to the data masking circuit to stops a corresponding data of the input data from being written to the plurality of memory banks; or
providing a disable signal as the mask control signal to the data masking circuit so as for the input data not to be masked.
7. The method of claim 5 , wherein the data masking circuit is disposed for each of the plurality of memory banks.
8. The method of claim 1 , wherein, when the control signal is used for inverting the input data, performing the data masking mode is disabled.
9. The method of claim 1 , wherein, when the control signal is used for masking the input data, performing the inverting mode is disabled.
10. The method of claim 1 , wherein the inverting circuit and the data mask circuit are included in a write circuit adjacent to a corresponding memory bank.
11. The method of claim 10 , wherein the write circuit includes a write driving circuit that drives an input/output line to write an output of the inverting circuit to the corresponding memory bank.
12. The method of claim 10 , wherein the write circuit includes a write driving circuit that drives an input/output line to write an output of the data mask circuit to the corresponding memory bank.
13. A method of controlling a memory, the method comprising:
receiving a control signal at a control terminal;
receiving an input data to be written to a plurality of memory banks via data terminals;
performing an inverting mode for inverting or non-inverting the input data, using an inverting circuit, based on a first mode register signal and the control signal; and
performing a data masking mode for masking the input data, using a data masking circuit, based on a second mode register signal and the control signal,
wherein the control signal is received from only one control terminal.
14. The method of claim 13 , wherein the control signal includes an inversion control signal.
15. The method of claim 13 , wherein the control signal includes a masking control signal.
16. The method of claim 13 , wherein the control signal includes an inversion control signal and a masking control signal.
17. The method of claim 13 , wherein the first mode register signal and the second mode register signal are stored at a mode register.
18. The method of claim 13 , wherein the control terminal includes a pad.
19. The method of claim 18 , wherein since the control signal needed to perform write data bus inversion and data masking are received via one terminal, a separate terminal does not need to be added.