Computer memory access

1. A computer memory access method, comprising:

receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion;

writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit, and reading a third data portion corresponding to the masked second data portion from the data storage unit of the computer memory by a reading unit;

producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion;

generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then

writing the generated parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.

2. The computer memory access method of claim 1 , wherein the unmasked first data portion and the masked second data portion are denoted by data mask signals.

3. The computer memory access method of claim 2 , wherein the unmasked first data portion is denoted by a data mask signal with a value of 0, and the masked second data portion is denoted by a data mask signal with a value of 1.

4. The computer memory access method of claim 3 , wherein the prefetching length is 64-bit, and each 8-bit of the external data in an order of lower bits to higher bits corresponds to one data mask signal,

wherein, when the value of the data mask signal denoting the n th 8-bit of the external data is 1, the masked second data portion of the external data is from the 8n−7 th bit to the 8n th bit,

wherein n is an integer, and 0<n<9, and

wherein, when merging,

if n=1, the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged,

if 1<n<8, the 1 st to the 8n−8 th bit and the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged, and

if n=8, the 1 st to the 8n−8 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged.

5. The computer memory access method of claim 3 , wherein the prefetching length is 64-bit, and each 8-bit of the external data in an order of lower bits to higher bits corresponds to one data mask signal,

wherein, when the value of the data mask signal denoting the m th 8-bit and the value of the data mask signal denoting the n th 8-bit of the external data are both 1, the masked second data portion of the external data are from the 8m−7 th bit to the 8m th bit and from the 8n−7 th bit to the 8n th bit,

wherein m and n are integers, and 0<m<n<9, and

wherein, when merging,

if m≠1 and n≠8, the 1 st to the 8(m−1) th bit, the 8m+1 th to the 8(n−1) th bit and the (8n+1) th to the 64 th bit of the external data and the data in the data storage unit of the memory are correspondingly merged,

if m=1 and n≠8, the 9 th to the 8(n−1) th bit and the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged,

if m≠1 and n=8, the 1 st to the 8(m−1) th bit and the 8m+1 th to the 56 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged, and

if m=1 and n=8, the 9 th to the 56 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged.

6. The computer memory access method of claim 1 , wherein the prefetching length is 32-bit, 64-bit or 128-bit.

7. The computer memory access method of claim 1 , wherein the error correction code encoding circuit is a Hamming code encoding circuit.

8. A computer memory access method comprising:

receiving external data;

determining whether there is data mask in the external data;

in response to determining that there is no data mask in the external data:

writing the external data to a data storage unit of a computer memory by a writing unit;

generating parity bits from the external data by an error correction code encoding circuit according to a given rule; and

respectively writing the external data and the parity bits to the data storage unit and a parity bit storage unit of the computer memory by the writing unit;

otherwise, in response to determining that there is data mask in the external data:

dividing the external data into an unmasked first data portion and a masked second data portion;

writing the unmasked first data portion to the corresponding data storage unit of the computer memory by a writing unit, and reading a third data portion corresponding to the masked second data portion from the data storage unit of the computer memory by a reading unit;

generating modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion;

generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and

writing the generated parity bits to the parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.

9. The computer memory access method of claim 8 , wherein the data mask signal is used to judge whether there is data mask in the external data.

10. The computer memory access method of claim 9 , wherein the unmasked first data portion is denoted by a data mask signal with a value of 0, and the masked second data portion is denoted by a data mask signal with a value of 1.

11. The computer memory access method of claim 9 , wherein the prefetching length is 64-bit, and each 8-bit of the external data in an order of lower bits to higher bits corresponds to one data mask signal,

wherein, when the value of the data mask signal denoting the n th 8-bit of the external data is 1, the masked second data portion of the external data is from the 8n−7 th bit to the 8n th bit,

wherein n is an integer, and 0<n<9, and

wherein, when merging,

if n=1, the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged,

if 1<n<8, the 1 st to the 8n−8 th bit and the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the memory are correspondingly merged, and

if n=8, the 1 st to the 8n−8 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged.

12. The computer memory access method of claim 9 , wherein the prefetching length is 64-bit, and each 8-bit of the external data in an order of lower bits to higher bits corresponds to one data mask signal,

wherein, when the value of the data mask signal denoting the m th 8-bit and the value of the data mask signal denoting the n th 8-bit of the external data are both 1, the masked second data portion of the external data is from the 8m−7 th bit to the 8m th bit and from the 8n−7 th bit to the 8n th bit,

wherein m and n are integers, and 0<m<n<9, and

wherein, when merging,

if m≠1 and n≠8, the 1 st to the 8(m−1) th bit, the 8m+1 th to the 8(n−1) th bit and the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the memory are correspondingly merged,

if m=1 and n≠8, the 9 th to the 8(n−1) th bit and the 8n+1 th to the 64 th bit of the external data and the data in the data storage unit of the memory are correspondingly merged,

if m≠1 and n=8, the 1 st to the 8(m−1) th bit and the 8m+1 th to the 56 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged, and

if m=1 and n=8, the 9 th to the 56 th bit of the external data and the data in the data storage unit of the computer memory are correspondingly merged.

13. The computer memory access method of claim 8 , wherein the prefetching length is 32-bit, 64-bit or 128-bit.

14. The computer memory access method of claim 8 , wherein the error correction code encoding circuit is a Hamming code encoding circuit.

15. A computer memory error correction method, comprising:

receiving external data;

determining whether there is data mask in the received external data;

in response to determining that there is a data mask:

writing an unmasked portion of the external data to a storage array of a computer memory and reading data corresponding to a masked portion of the external data from the storage array; then

merging the data written to the storage array and the data read from the storage array to produce merged data;

generating corresponding parity bits from the merged data by an error correction code encoding circuit according to a given rule; and

writing the merged data and the corresponding parity bits to the storage array in complete substitution of previous information stored in the storage array;

otherwise, in response to determining that there is no data mask in the received external data:

directly writing the received external data to the storage array;

generating corresponding parity bits from the received external data by an error correction code encoding circuit according to a given rule; and

writing the external data and the corresponding parity bits to the storage array in complete substitution of previous information stored in the storage array.

16. A computer memory error correction method, comprising:

receiving external data including data mask;

writing an unmasked portion of the received external data to a storage array of a computer memory, while reading data corresponding to a masked portion of the received external data from the storage array;

producing modified data by merging the external data written to the storage array and the data read from the storage array;

generating corresponding parity bits from the modified data by an error correction code encoding circuit according to a given rule; and then

writing the modified data and the corresponding parity bits to the storage array in complete substitution of previous information stored in the storage array.