IP Library Granted Patent US 9,653,040
Granted Patent B2
US 9,653,040 · App. 15/359,401 · Granted May 16, 2017

Display driver capable of driving multiple display interfaces

Inventors: Aruna Kumar (Bangalore, IN); Prakash K. Radhakrishnan (Portland, OR); Pravas Pradhan (Bangalore, IN); Sunil Kumar C R (Bangalore, IN); Vikas J (Bangalore, IN)
Assignee: Intel Corporation
G09G5/006G09G2300/08G09G2310/027G09G2330/021G09G2330/028G09G2370/08G09G2370/12
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Quick Facts
Patent No.
US 9,653,040
App. No.
15/359,401
Granted
May 16, 2017
Kind
B2
Abstract

A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.

Claims (7)

1. A method, comprising:

selecting one from a first, second, third, and fourth display interface, said selected one display interface having a lower power than the unselected ones of the display interfaces;

disabling transistors of a high speed portion of a display interface driver in response to said selecting, said disabling including providing bias voltages to gates of said transistors of said high speed portion to prevent gate dielectric breakdown of said transistors while a low speed portion of said display interface driver is driving data signals of said selected one display interface; and,

driving data signals of said selected one display interface through an output, wherein voltages of said data signals also reach said transistors.

2. The method of claim 1 wherein said first, second, third, fourth, and a fifth display interface supported by said display interface driver are DP, HDMI, eDP, high speed MIPI DSI, and low power MIPI DSI.

3. The method of claim 1 wherein said transistors have a thinner gate dielectric than transistors that are driving said data signals.

4. The method of claim 1 further comprising providing a first one of said bias voltages to a p type pull-up transistor and providing a second one of said bias voltages to an n type pull-up transistor.

Continuity (2)
Continuation 14142320 · Dec 27, 2013
Related Publication 20170076689A1 · Mar 16, 2017