Multilayer ceramic capacitor and board having the same
A multilayer ceramic capacitor may include a ceramic body having first to third dielectric layers, first and third internal electrodes disposed to be partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed to be partially exposed to a lower surface of the ceramic body, internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body, first and third external electrodes disposed on the ceramic body to be connected to the first and third internal electrodes, second and fourth external electrodes disposed to be connected to the second and fourth internal electrodes. The first and third external electrodes are electrically connected to each other by the internal resistance electrodes.
1. A multilayer ceramic capacitor comprising:
a ceramic body having first to third dielectric layers layered in a width direction of the ceramic body, first internal electrodes disposed on the first dielectric layers and partially exposed to an upper surface of the ceramic body, second internal electrodes disposed on the second dielectric layers and partially exposed to a lower surface of the ceramic body, third internal electrodes disposed on the first dielectric layers and partially exposed to the upper surface of the ceramic body, fourth internal electrodes disposed on the second dielectric layers and partially exposed to the lower surface of the ceramic body and internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body;
a first external electrode disposed on the upper surface of the ceramic body and connected to the first internal electrodes;
a second external electrode disposed on the lower surface of the ceramic body and connected to the second internal electrodes;
a third external electrode disposed on the upper surface of the ceramic body, connected to the third internal electrodes, and disposed to be spaced apart from the first external electrode; and
a fourth external electrode disposed on the lower surface of the ceramic body, connected to the fourth internal electrodes, and disposed to be spaced apart from the second external electrode,
wherein the first and third external electrodes are electrically connected to each other by the internal resistance electrodes.
2. The multilayer ceramic capacitor of claim 1 , wherein conductivity, widths, or lengths of the internal resistance electrodes are adjusted to adjust equivalent series resistance (ESR).
3. The multilayer ceramic capacitor of claim 1 , wherein the first and third internal electrodes are disposed on the same first dielectric layers while being spaced apart from each other, and
the second and fourth internal electrodes are disposed on the same second dielectric layers while being spaced apart from each other.
4. The multilayer ceramic capacitor of claim 1 , wherein the first and third internal electrodes are disposed on different first dielectric layers, and
the second and fourth internal electrodes are disposed on different second dielectric layers.
5. The multilayer ceramic capacitor of claim 1 , further comprising dummy electrodes disposed on at least portions of the first to third dielectric layers and exposed to end surfaces of the ceramic body in a length direction of the ceramic body.
6. The multilayer ceramic capacitor of claim 1 , further comprising a dummy electrode disposed on at least a portion of the first to third dielectric layers and exposed to the upper surface of the ceramic body.
7. The multilayer ceramic capacitor of claim 1 , further comprising a mark formed on a portion of a side surface of the ceramic body close to the upper surface of the ceramic body.
8. A board having a multilayer ceramic capacitor, comprising:
a circuit board having first and second electrode pads disposed on the circuit board; and
a multilayer ceramic capacitor disposed on the circuit board,
wherein the multilayer ceramic capacitor includes:
a ceramic body having first to third dielectric layers layered in a width direction of the ceramic body, first internal electrodes disposed on the first dielectric layers and partially exposed to an upper surface of the ceramic body, second internal electrodes disposed on the second dielectric layers and partially exposed to a lower surface of the ceramic body, third internal electrodes disposed on the first dielectric layers and partially exposed to the upper surface of the ceramic body, fourth internal electrodes disposed on the second dielectric layers and partially exposed to the lower surface of the ceramic body and internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body;
a first external electrode disposed on the upper surface of the ceramic body and connected to the first internal electrodes;
a second external electrode disposed on the lower surface of the ceramic body and connected to the second internal electrodes;
a third external electrode disposed on the upper surface of the ceramic body, connected to the third internal electrodes, and disposed to be spaced apart from the first external electrode; and
a fourth external electrode disposed on the lower surface of the ceramic body, connected to the fourth internal electrodes, and disposed to be spaced apart from the second external electrode,
the first and third external electrodes being electrically connected to each other by the internal resistance electrodes.
9. The board having a multilayer ceramic capacitor of claim 8 , wherein conductivity, widths, or lengths of the internal resistance electrodes are adjusted to adjust ESR.
10. The board having a multilayer ceramic capacitor of claim 8 , wherein the first and third internal electrodes are disposed on the same first dielectric layers while being spaced apart from each other, and
the second and fourth internal electrodes are disposed on the same second dielectric layers while being spaced apart from each other.
11. The board having a multilayer ceramic capacitor of claim 8 , wherein the first and third internal electrodes are disposed on different first dielectric layers, and
the second and fourth internal electrodes are disposed on different second dielectric layers.
12. The board having a multilayer ceramic capacitor of claim 8 , further comprising dummy electrodes disposed on at least portions of the first to third dielectric layers and exposed to end surfaces of the ceramic body in a length direction of the ceramic body.
13. The board having a multilayer ceramic capacitor of claim 8 , further comprising a dummy electrode disposed on at least a portion of the first to third dielectric layers and exposed to the upper surface of the ceramic body.
14. The board having a multilayer ceramic capacitor of claim 8 , wherein the multilayer ceramic capacitor further includes a mark formed on a portion of a side surface of the ceramic body close to the upper surface of the ceramic body.