Gallium nitride nanowire based electronics
GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.
1. A semiconductor device, comprising:
a substrate;
a plurality of III-nitride semiconductor nanowires extending substantially perpendicular to a major surface of the substrate;
a plurality of discrete III-nitride semiconductor mesas, wherein each of the plurality of mesas located around and over each of the plurality of the nanowires; and
at least one electrode located over each of the plurality of discrete III-nitride semiconductor mesas,
wherein:
an insulating growth mask is located over the substrate;
the plurality of III-nitride semiconductor nanowires protrude from openings in the growth mask;
each mesa has a substantially planar c-plane upper surface;
each mesa contains a III-nitride displacing layer whose upper surface forms the substantially planar c-plane upper surface;
the displacing layer comprises a GaN layer, a ternary layer or a quaternary layer and wherein the substantially planar c-plane upper surface is offset from an upper tip of a nanowire located in the mesa;
the nanowire is not part of an active device region of the device and the nanowire is not electrically connected to an outside circuit; and
the displacing layer is a low doped semiconductor or semi-insulating layer which is not part of the active device region of the device.
2. The device of claim 1 , wherein each mesa has a resistivity of above 10 5 ohm*cm.
3. The device of claim 1 , wherein the substantially planar c-plane upper surface is substantially free of threading dislocations, and wherein at least 90% of the plurality of discrete III-nitride semiconductor mesas have no threading dislocations in the substantially planar c-plane upper surfaces.
4. The device of claim 1 , further comprising at least one semiconductor active device layer located over the substantially planar c-plane upper surface, wherein the at least one semiconductor active device layer has an impurity content of less than 5×10 16 cm −2 and is substantially free of threading dislocations.
5. The device of claim 1 , wherein:
the plurality of semiconductor nanowires comprise GaN nanowires;
the substrate comprises an insulating or semi-insulating substrate;
the semiconductor mesa comprises a discrete GaN mesa having sloped side walls; and
the device comprises a diode or a transistor.
6. The device of claim 1 , wherein the device comprises a DC to AC power inverter comprising a plurality of transistors and diodes electrically connected in series or in parallel.
7. The device of claim 1 , wherein the device comprises a plurality of transistors having gates connected to a common gate line, further comprising a field plate covering a gate electrode or the gate electrode and a source electrode of the transistor.
8. The device of claim 1 , wherein the device comprises a hybrid device comprising a HEMT in at least one of the plurality of mesas and a diode in at least one other of the plurality of mesas over the substrate.
9. The device of claim 1 , wherein each of the plurality of mesas comprise a single nanowire.
10. The device of claim 1 , wherein the plurality of mesas are located on the substrate and the at least one electrode extends over a plurality of mesas located on the substrate.
11. The device of claim 1 , wherein all of the mesas on the substrate are located around and over a nanowire and include the at least one electrode located over the mesa.