IP Library Granted Patent US 9,658,986
Granted Patent B2
US 9,658,986 · App. 14/167,253 · Granted May 23, 2017

Advanced computational processes and methods of using the same

Inventors: Yi Ge (Bunkyo, JP); Noboru Kobayashi (Tokorozawa, JP); Hiroshi Hatano (Kawasaki, JP); Yasuhiro Oyama (Yokohama, JP)
Assignee: FUJITSU LIMITED
G06F17/16G06F9/30014G06F9/30032G06F9/30036H03M7/24
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Quick Facts
Patent No.
US 9,658,986
App. No.
14/167,253
Granted
May 23, 2017
Kind
B2
Abstract

A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit.

Claims (41)

1. A data processing apparatus comprising:

a computing circuit that performs a matrix computation between data streams whose unit data is of a matrix format;

a determining unit that: for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value, by obtaining one or more element sets, each having a corresponding element count and each being a series of elements obtained by the matrix computation by the computing circuit, and determining based on the value of each element included in the element set, an exponent value for the element set to express elements of the element set as floating decimal point values, the element count being a unit data length, the unit data length corresponding to an instruction and being a length of a unit of the matrix;

wherein the determining unit includes:

a determining circuit that, with respect to each element set having a corresponding element count where a total count of elements included in a series of elements is an upper limit, determines from the head of the series of elements and for each element set and based on the value of each element included in the element set, the exponent value for the element set to express each element of the element set as a floating decimal point value; and

a selecting circuit that, with respect to each element included in the series of elements, selects from among the exponent values determined for each element set by the determining circuit, the exponent value for the element set;

a converting unit that converts the value of each element included in the series of elements into a significand value of the element, according to the exponent value determined by the determining unit; and

wherein the converting unit includes a shifting circuit that, for each element included in the series of elements, converts the value of the element into the significand of the element according to the exponent value selected for the element set by the selecting circuit; and

an output circuit that:

correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit; and

correlates and outputs the exponent value determined for each element set by the determiner and the value of each element included in the element set after conversion by the converter.

2. The data processing apparatus according to claim 1 , wherein the determining unit determines as the exponent value for each matrix, the exponent value for expressing, as a floating decimal point value, the element whose absolute value is greatest among the elements included in the matrix.

3. The data processing apparatus according to claim 1 , wherein

the stream data includes an array of the matrices after the conversion in which the value of each element has been converted by the converting unit and an array of the exponent values determined for each matrix by the determining unit, and

the computing circuit, when performing a matrix addition computation between the data streams, performs the matrix addition computation between the data streams by shifting the value of each element included in any one among first and second matrices corresponding to the data streams, based on a difference of first and second exponent values corresponding to the data streams.

4. The data processing apparatus according to claim 3 , wherein the computing circuit, based on a value obtained by subtracting the first exponent value from the second exponent value, shifts the first matrix when the obtained value is positive and shifts the second matrix, based on the value when the obtained value is negative.

5. The data processing apparatus according to claim 1 , wherein the converting unit includes the shifting circuit that, for each element set of the element count that is the unit data length and when among a first mode and a second mode, the first mode has been selected, converts the value of each element included in the element set into a significand value of the element according to the exponent value determined for the element set by the determining unit, and when the second mode has been selected, converts the value of each element included in the series of elements into a significand of the element according to an exponent value input for the series of elements.

6. The data processing apparatus according to claim 1 , wherein

the determining unit, from the head of the series of elements and for each element set of the element count that is the unit data length, determines as the exponent value for the element set, the exponent value that is greatest among the exponent values of the elements included in the element set, when each of the elements included in the series of elements is expressed as a floating decimal point value, and

the converting unit, for each element set, converts the significand value of each element included in the element set into the significand of each element, according to a conversion exponent value calculated by subtracting the exponent value of the element from the greatest exponent value.

7. The data processing apparatus according to claim 1 , wherein the element count is a power of the number two.

8. A data processing method that is executed by a computer, the data processing method comprising:

performing a matrix computation by a computing circuit between data streams whose unit data is of a matrix format;

determining for each matrix obtained by the matrix computation by the computing circuit and based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value, by obtaining one or more element sets, each having a corresponding element count and each being a series of elements obtained by the matrix computation by the computing circuit, and determining based on the value of each element included in the element set, an exponent value for the element set to express elements of the element set as floating decimal point values, the element count being a unit data length, the unit data length corresponding to an instruction and being a length of a unit of the matrix;

wherein the step of determining includes:

with respect to each element set having a corresponding element count where a total count of elements included in a series of elements is an upper limit, determining by a determining circuit from the head of the series of elements and for each element set and based on the value of each element included in the element set, the exponent value for the element set to express each element of the element set as a floating decimal point value; and

with respect to each element included in the series of elements, selecting by a selecting circuit from among the exponent values determined for each element set, the exponent value for the element set;

converting the value of each element included in the series of elements into a significand value of the element, according to the exponent value determined at the determining, wherein the step of converting includes, for each element included in the series of elements, converting by a shifting circuit the value of the element into the significand of the element according to the exponent value selected for the element set by the selecting circuit; and

correlating and outputting the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted at the converting; and

correlating and outputting the exponent value determined for each element set and the value of each element included in the element set after conversion.

9. The data processing method according to claim 8 , wherein the element count is a power of the number two.

10. A non-transitory, computer-readable recording medium that stores a data processing program that causes a computer to execute a process comprising:

performing a matrix computation by a computing circuit between data streams whose unit data is of a matrix format;

determining for each matrix obtained by the matrix computation by the computing circuit and based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value, by obtaining one or more element sets, each having a corresponding element count and each being a series of elements obtained by the matrix computation by the computing circuit, and determining based on the value of each element included in the element set, an exponent value for the element set to express elements of the element set as floating decimal point values, the element count being a unit data length, the unit data length corresponding to an instruction and being a length of a unit of the matrix;

wherein the step of determining includes:

with respect to each element set having a corresponding element count where a total count of elements included in a series of elements is an upper limit, determining by a determining circuit from the head of the series of elements and for each element set and based on the value of each element included in the element set, the exponent value for the element set to express each element of the element set as a floating decimal point value; and

with respect to each element included in the series of elements, selecting by a selecting circuit from among the exponent values determined for each element set by the determining circuit, the exponent value for the element set;

converting the value of each element included in the series of elements into a significand value of the element, according to the exponent value determined at the determining, wherein the step of converting includes, for each element included in the series of elements, converting by a shifting circuit the value of the element into the significand of the element according to the exponent value selected for the element set by the selecting circuit; and

correlating and outputting the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted at the converting; and

correlating and outputting the exponent value determined for each element set and the value of each element included in the element set after conversion.

11. The non-transitory, computer-readable recording medium according to claim 10 , wherein the element count is a power of the number two.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2016
From: SOCIONEXT, INC.
To: FUJITSU LIMITED
Reel/Frame 039318/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2015
From: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED; SOCIONEXT INC.
Reel/Frame 035481/0271 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND INVENTOR'S NAME PREVIOUSLY RECORDED ON REEL 032102 FRAME 0648. ASSIGNOR(S) HEREBY CONFIRMS THE EXECUTED ASSIGNMENT. Recorded Feb 24, 2014
From: GE, YI; KOBAYASHI, NOBORU; HATANO, HIROSHI; OYAMA, YASUHIRO
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 032435/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2014
From: GE, YI; KOBAYASHI, NOBURO; HATANO, HIROSHI; OYAMA, YASUHIRO
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 032102/0648 →
Priority Claims (2)
JP 2013-029464 · Feb 18, 2013 · national
JP 2013-257371 · Dec 12, 2013 · national
Continuity (1)
Related Publication 20140237010A1 · Aug 21, 2014