IP Library Granted Patent US 9,666,792
Granted Patent B2
US 9,666,792 · App. 14/824,507 · Granted May 30, 2017

Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) elements

Inventors: Wei-Chuan Chen (San Diego, CA); Yu Lu (San Diego, CA); Chando Park (Irvine, CA); Seung Hyuk Kang (San Diego, CA)
Assignee: QUALCOMM Incorporated
H01L43/12H01L27/222H01L43/02H01L43/08
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Quick Facts
Patent No.
US 9,666,792
App. No.
14/824,507
Granted
May 30, 2017
Kind
B2
Abstract

Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.

Claims (57)

1. A method of fabricating a magnetic tunnel junction (MTJ) in a semiconductor wafer, comprising:

providing an MTJ stack-up on a substrate in the semiconductor wafer, the MTJ stack-up comprising a pinned layer disposed above a bottom electrode on the substrate, a free layer disposed above the pinned layer, a tunnel barrier disposed between the pinned layer and the free layer, and a hard mask disposed above the free layer;

forming at least one MTJ from the MTJ stack-up; and

etching the hard mask in the MTJ stack-up to fabricate the free layer smaller in width than the pinned layer in the MTJ stack-up, comprising:

rotating the semiconductor wafer to angularly rotate the MTJ stack-up with reference to an ion beam source; and

during the rotating of the semiconductor wafer for a revolution:

directing an ion beam from the ion beam source at a first angle of incidence towards the hard mask when the MTJ stack-up is disposed at a first rotational angle of the revolution with reference to the ion beam source; and

directing the ion beam from the ion beam source at a second angle of incidence in the revolution different from the first angle of incidence towards the hard mask when the MTJ stack-up is disposed at a second rotational angle of the revolution different from the first rotational angle with reference to the ion beam source.

2. The method of claim 1 , comprising:

directing the ion beam from the ion beam source at the first angle of incidence between approximately 55 degrees and 75 degrees towards the hard mask when the MTJ stack-up is disposed at the first rotational angle of the revolution with reference to the ion beam source; and

directing the ion beam from the ion beam source at the second angle of incidence between approximately 55 degrees and 75 degrees in the revolution different from the first angle of incidence towards the hard mask when the MTJ stack-up is disposed at the second rotational angle of the revolution different from the first rotational angle with reference to the ion beam source.

3. The method of claim 2 , comprising:

directing the ion beam from the ion beam source at the first angle of incidence between approximately 56.3 degrees and 73.5 degrees towards the hard mask when the MTJ stack-up is disposed at the first rotational angle of the revolution with reference to the ion beam source.

4. The method of claim 2 , comprising:

directing the ion beam from the ion beam source at the first angle of incidence of the ion beam source between approximately 55 degrees and 75 degrees towards the hard mask when the MTJ stack-up is disposed at the first rotational angle between approximately 0 degrees and 26 degrees of the revolution with reference to the ion beam source.

5. The method of claim 2 , comprising:

directing the ion beam from the ion beam source at the first angle of incidence of the ion beam source between approximately 75 degrees and 64 degrees towards the hard mask when the MTJ stack-up is disposed at the first rotational angle between approximately 27 degrees and 45 degrees of the revolution with reference to the ion beam source.

6. The method of claim 1 , further comprising not etching the pinned layer during the directing of the ion beam at the first angle of incidence towards the hard mask, and the directing of the ion beam at the second angle of incidence towards the hard mask.

7. The method of claim 1 , further comprising substantially removing a free layer footing formed in the free layer.

8. The method of claim 1 , further comprising directing an ion beam towards the MTJ stack-up to etch away a central area of the MTJ stack-up to form at least two adjacent MTJs between an etched away central area of the MTJ stack-up.

9. The method of claim 1 , further comprising trimming a free layer footing formed in the free layer to an etch stop formed by the tunnel barrier.

10. The method of claim 9 , wherein trimming the free layer footing comprises directing an ion beam substantially normal to the hard mask and to the etch stop formed by the tunnel barrier.

11. The method of claim 9 , wherein trimming the free layer footing comprises directing a reactive ion etch (RIE) substantially normal to the hard mask and to the etch stop formed by the tunnel barrier.

12. The method of claim 1 , further comprising disposing a passivation layer on the MTJ stack-up before directing the ion beam from the ion beam source at the first angle of incidence towards the hard mask when the MTJ stack-up is disposed at the first rotational angle.

13. The method of claim 12 , wherein directing the ion beam from the ion beam source at the first angle of incidence towards the hard mask when the MTJ stack-up is disposed at the first rotational angle etches a portion of the passivation layer adjacent to the hard mask and the free layer.

14. The method of claim 1 , wherein directing the ion beam at the first angle of incidence comprises directing the ion beam from the ion beam source at the first angle of incidence towards the hard mask and the free layer when the MTJ stack-up is disposed at the first rotational angle to etch the hard mask and the free layer in the MTJ stack-up, wherein a free layer footing is formed in the free layer.

15. The method of claim 1 , wherein directing the ion beam comprises directing the ion beam from the ion beam source at the first angle of incidence towards the hard mask when the MTJ stack-up is disposed at the first rotational angle to etch only the hard mask in the MTJ stack-up.

16. A magnetic tunnel junction (MTJ) comprising:

a first electrode;

a second electrode;

a pinned layer of a pinned layer width disposed between the first electrode and the second electrode;

a free layer between the first electrode and the pinned layer, the free layer having a free layer width smaller than the pinned layer width;

a tunnel barrier disposed between the pinned layer and the free layer; and

a shadow-effect compensated ion beam etched hard mask disposed above the free layer between the free layer and the first electrode.

17. The MTJ of claim 16 , wherein the free layer is comprised of a shadow-effect compensated ion beam etched free layer.

18. The MTJ of claim 16 , wherein the shadow-effect compensated ion beam etched hard mask is an only shadow-effect compensated ion beam etched layer.

19. The MTJ of claim 16 , wherein the free layer is substantially free of a free layer footing.

20. The MTJ of claim 16 , wherein the free layer has a substantially symmetrical radius.

21. The MTJ of claim 16 , further comprising an inter-metal dielectric (IMD) layer disposed below the pinned layer.

22. The MTJ of claim 16 provided in a magnetic random access memory (MRAM) bit cell.

23. The MTJ of claim 16 integrated into an integrated circuit (IC).

24. The MTJ of claim 16 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

25. A magnetic random access memory (MRAM) system, comprising:

an MRAM array provided in a semiconductor die, the MRAM array comprising a plurality of MRAM bit cells; and

each of the plurality of MRAM bit cells comprising:

an access transistor comprising a gate coupled to a write line, a first electrode, and a second electrode; and

a magnetic tunnel junction (MTJ), comprising:

a first electrode layer coupled to a bitline;

a second electrode layer coupled to an electrode of the access transistor;

a tunnel barrier between the first electrode layer and the second electrode layer;

a pinned layer having a pinned layer width, the pinned layer disposed between the second electrode and the tunnel barrier;

a free layer between the first electrode and the tunnel barrier, the free layer having a free layer width smaller than the pinned layer width; and

a shadow-effect compensated ion beam etched hard mask disposed above the free layer between the free layer and the first electrode layer.

26. The MRAM system of claim 25 , wherein the free layer in the MTJ in each of the plurality of MRAM bit cells is comprised of a shadow-effect compensated ion beam etched free layer.

27. The MRAM system of claim 25 , wherein the shadow-effect compensated ion beam etched hard mask in the MTJ in each of the plurality of MRAM bit cells is an only shadow-effect compensated ion beam etched layer.

28. The MRAM system of claim 25 , wherein the free layer in the MTJ in each of the plurality of MRAM bit cells is substantially free of a free layer footing.

29. The MRAM system of claim 25 , wherein the free layer in the MTJ in each of the plurality of MRAM bit cells has a substantially symmetrical radius.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2015
From: CHEN, WEI-CHUAN; LU, YU; PARK, CHANDO; KANG, SEUNG HYUK
To: QUALCOMM INCORPORATED
Reel/Frame 036830/0470 →
Continuity (1)
Related Publication 20170047510A1 · Feb 16, 2017