Semiconductor memory device and refresh control method thereof
A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command.
1. A semiconductor memory device comprising:
a memory bank including a plurality of word lines;
a refresh operation control unit that performs a first refresh operation to a first adjacent word line group of a target word line of the plurality of word lines for at least two times, and performs a second refresh operation to a second adjacent word line group of the target word line for at least two times after the first refresh operation, in response to a smart refresh command;
a normal command generation unit that generates a normal refresh command in response to a refresh command; and
a smart command generation unit that counts the refresh command and generates the smart refresh command whenever the refresh command is counted a first predetermined number of times,
wherein the normal refresh command is deactivated when the smart refresh command is activated,
wherein the first adjacent word line group includes the (N−1) th and (N+1) th word lines and the second adjacent word line group includes the (N−2) th and (N+2) th word lines when the target word line corresponds to the N th word line,
wherein the normal command generation unit counts a refresh command and generates a normal refresh command which is activated in each predetermined cycle.
2. The semiconductor memory device of claim 1 , wherein the first adjacent word line group includes a word line first adjacent to the target word line, and the second adjacent word line group includes a word line second adjacent to the target word line, among the plurality of word lines.
3. The semiconductor memory device of claim 1 , wherein the smart command generation unit counts the refresh command to activate the smart refresh command for executing a first smart mode in each first predetermined cycle, and counts the refresh command to activate the smart refresh command for executing a second smart mode in each second predetermined cycle.
4. The semiconductor memory device of claim 1 , wherein the refresh operation control unit sequentially accesses the plurality of word lines in response to the normal refresh command.
5. The semiconductor memory device of claim 1 , wherein the refresh operation control unit comprises:
a normal address generation section that counts the normal refresh command and generating a normal refresh address;
a target row information generation section that receives a bank address, a row command, and a row address, and generating target row information on the target word line;
a smart address generation section that receives the smart refresh command and the target row information and generates a first adjacent address for the first adjacent word line group or a second adjacent address for the second word line group; and
a word line driving section that drives word lines corresponding to the normal refresh address and the first and second adjacent addresses, among the plurality of word lines.
6. The semiconductor memory device of claim 5 , wherein the smart address generation section comprises:
a counting part that counts the smart refresh command and generating a control signal;
an address latching part that latches the target row information and outputting a latched address; and
an address output part that outputs a first adjacent address group of the latched address or a second adjacent address group of the latched address in response to the control signal.
7. The semiconductor memory device of claim 6 , wherein the counting part counts the smart refresh command and activates the control signal when the smart refresh command is counted a second predetermined number of times.
8. The semiconductor memory device of claim 6 , wherein the address output part outputs the first adjacent address group when the control signal is deactivated and outputs the second adjacent address group when the control signal is activated.
9. A semiconductor memory device comprising:
a memory bank including a plurality of word lines;
a smart command generation unit that counts a refresh command and generating a smart refresh command which is activated in a predetermined cycle;
a refresh operation control unit that counts the smart refresh command, performs a refresh operation to a first word lines most adjacent to a target word line of the plurality of word lines for at least two times, and performs the refresh operation to a second word lines second adjacent to the target word line for at least two times after the refresh operation of the first word lines; and
a normal command generation unit that generates a normal refresh command in response to the refresh command and deactivates the normal refresh command when the smart refresh command is activated
wherein the first word lines include the (N−1) th and (N+1) th word lines and the second word lines include the (N−2) th and (N+2) th word lines when the target word line corresponds to the N th word line,
wherein the refresh operation control unit comprises:
a normal address generation section that counts the normal refresh command and generating a normal refresh address;
a target row information generation section that receives a bank address, a row command, and a row address, and generating target row information on the target word line;
a smart address generation section that receives the smart refresh command and the target row information and generates a first adjacent address for the first word line or
a second adjacent address for the second word line; and
a word line driving section that drives word lines corresponding to the normal refresh address and the first and second adjacent addresses, among the plurality of word lines.
10. The semiconductor memory device of claim 9 , wherein the smart address generation section comprises:
a counting part that counts the smart refresh command and generating a control signal;
an address latching part that latches the target row information and outputting a latched address; and
an address output part that outputs a first adjacent address group of the latched address or a second adjacent address group of the latched address in response to the control signal.
11. The semiconductor memory device of claim 10 , wherein the counting part counts the smart refresh command and activates the control signal when the smart refresh command is counted a predetermined number of times.
12. The semiconductor memory device of claim 10 , wherein the address output part outputs the first adjacent address group when the control signal is deactivated and outputs the second adjacent address group when the control signal is activated.
13. A refresh operation method of a semiconductor memory device, comprising:
detecting a target word line of a plurality of word lines;
performing a smart refresh operation to a first pair of word lines first adjacent to the target word line, among the plurality of word lines, for at least two times in response to a refresh command; and
performing the smart refresh operation to a second pair of word lines second adjacent to the target word line, among the plurality of word lines for at least two times, in response to the refresh command, after the performing of the smart refresh operation for the first pair of word lines;
sequentially performing a normal refresh operation for the plurality of word lines in response to the refresh command,
wherein the first pair of word lines include the (N−1) th and (N+1) th word lines and the second pair of word lines include the (N−2) th and (N+2) th word lines when the target word line corresponds to the N th word line
wherein the smart refresh operation is performed in response to a smart refresh command whenever the refresh command is counted a first predetermined number of times,
wherein the normal refresh operation is deactivated when the smart refresh command is activated,
wherein the normal refresh operation is performed in response to a normal refresh command generated by counting a refresh command and generates a normal refresh command and the normal refresh command is activated in each predetermined cycle.
14. The refresh operation method of claim 13 , further comprising:
updating the target word line whenever the smart refresh operation is performed.