Photosensitive imaging devices and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.
1. A photosensitive imager device, comprising:
a plurality of semiconductor devices including at least one semiconductor substrate having a light incident side and multiple doped regions forming at least one junction;
a textured region coupled to the light incident side of the at least one semiconductor substrate and positioned to interact with electromagnetic radiation; said textured region having structures with sizes in a range of about 50 nm to about 20 microns, and
at least one isolation feature operable to isolate the plurality of semiconductor devices from each other.
2. The device of claim 1 , wherein the at least one isolation feature is operable to electrically isolate the plurality of semiconductor devices from each other.
3. The device of claim 1 , wherein the at least one isolation feature is operable to optically isolate the plurality of semiconductor devices from each other.
4. The device of claim 1 , wherein the at least one isolation feature is a deep trench isolation feature.
5. The device of claim 1 , wherein the at least one isolation feature is a shallow trench isolation feature.
6. The device of claim 1 , wherein the at least one isolation feature includes a material selected from the group consisting of, metals, oxides, polymers, or combinations thereof.
7. The device of claim 1 , wherein the at least one isolation feature includes a reflecting material.
8. The device of claim 1 , further comprising a reflective layer coupled to the at least one semiconductor substrate and positioned to interact with electromagnetic radiation.
9. The device of claim 8 , wherein the reflective layer includes a material selected from the group consisting of metal, oxide, or combinations thereof.
10. The device of claim 8 , wherein the reflective layer is a Bragg reflector.
11. The device of claim 1 , wherein the at least one semiconductor substrate is epitaxially grown.
12. The device of claim 1 , further comprising at least on electrical transfer element functionally coupled to the plurality of semiconductor devices.
13. The device of claim 1 , wherein the at least one semiconductor substrate is comprised of silicon.
14. The device of claim 1 , wherein the textured region is formed by a technique selected from the group consisting of lasing, chemical etching, anisotropic etching, isotropic etching, nanoimprinting, additional material deposition, and combinations thereof.
15. The device of claim 1 , wherein the photosensitive imager device is a backside illuminated imager device.
16. The device of claim 1 , wherein the photosensitive imager device is a front side illuminated imager device.
17. The device of claim 1 , further comprising a second textured region coupled to the semiconductor substrate opposite the light incident side.
18. The device of claim 1 , wherein said textured region includes a plurality of nanocrystallites having sizes in a range of about 10 nanometers to about 50 nanometers.
19. The device of claim 1 , wherein said textured region includes grained polysilicon material.
20. The device of claim 1 , further comprising a passivation region electrically isolating the textured region from the doped regions.
21. The device of claim 20 , wherein said passivation region includes an oxide.
22. The device of claim 1 , wherein said textured region comprises an amorphous layer.
23. The device of claim 22 , wherein said amorphous layer comprises amorphous silicon.