Integrated circuit with well and substrate contacts

1. An integrated circuit, comprising:

standard cells arranged in rows and columns; and

tap cells arranged in rows and columns, the tap cells each comprising:

a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate; and

a well region in the substrate, wherein the well region has a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate,

wherein

the integrated circuit comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity,

each row of the first quantity of rows of tap cells comprises at least one well contact,

each row of tap cells of the second quantity of tap cells comprises at least one substrate contact, and

a quantity of well contacts is greater than a quantity of substrate contacts.

2. The integrated circuit of claim 1 , wherein a row of standard cells is between two rows of tap cells.

3. The integrated circuit of claim 1 , wherein a column of standard cells and tap cells comprises alternating standard cells and tap cells.

4. The integrated circuit of claim 1 , wherein the well region is a first well region and the standard cells each comprise:

the substrate; and

a second well region having the second dopant type and a depth less than the thickness of the substrate.

5. The integrated circuit of claim 4 , wherein the first well region is electrically isolated from the second well region.

6. The integrated circuit of claim 1 , wherein

the substrate contacts of the tap cells included in the second quantity of rows of tap cells are separated by a distance greater than a maximum distance set by a design rule and less than twice the maximum distance set by the design rule, and

the design rule is a rule established by an integrated circuit design system specifying the maximum distance between substrate contacts to prevent latchup.

7. The integrated circuit of claim 1 , wherein the tap cells have a cell height and the well region of at least one tap cell has a height equal to about the cell height.

8. The integrated circuit of claim 1 , wherein the first dopant type is a p-type dopant and the second dopant type is an n-type dopant.

9. The integrated circuit of claim 1 , wherein the first dopant type is an n-type dopant and the second dopant type is a p-type dopant.

10. The integrated circuit of claim 1 , wherein a width of at least one tap cell is less than a width of an adjacent standard cell.

11. A method of forming an integrated circuit, comprising:

forming rows and columns of tap cells, each tap cell being formed by implanting a dopant in a substrate to form a well region, wherein a dopant type of the substrate is different from a dopant type of the well region; and

forming rows and columns of standard cells,

wherein

a first quantity of rows of tap cells is formed having at least one well contact in each row of the first quantity of rows of tap cells,

a second quantity of rows of tap cells less than the first quantity is formed having at least one substrate contact in each row of the second quantity of rows of tap cells, and

a greater quantity of well contacts than a quantity of substrate contacts are formed.

12. The method of claim 11 , wherein a row of standard cells is formed between two rows of tap cells.

13. The method of claim 11 , wherein a column of tap cells is formed having spaces available between the tap cells in which a column of standard cells is formed, thereby forming a column of standard cells and tap cells comprising alternating standard cells and tap cells.

14. The method of claim 11 , wherein the well region is a first well region and the standard cells are each formed by:

forming a second well region in the substrate, the second well region being formed in the substrate in a position electrically isolated from the first well region, and the second well region having a same dopant type as the first well region.

15. The method of claim 11 , further comprising:

forming the substrate contacts of the tap cells included in the second quantity of rows of tap cells in positions separated by a distance greater than a maximum distance set by a design rule and less than twice the maximum distance set by the design rule,

wherein the design rule is a rule established by an integrated circuit design system specifying the maximum distance between substrate contacts to prevent latchup.

16. The method of claim 11 , wherein the tap cells are formed having a cell height and the well region of at least one tap cell is formed having a height equal to about the cell height.

17. The method of claim 11 , wherein the implanted dopant is a p-type dopant.

18. The method of claim 11 , wherein the implanted dopant is an n-type dopant.

19. The method of claim 11 , wherein at least one tap cell having a first width is formed adjacent to a standard cell having a second width, the second width being greater than the first width.

20. An integrated circuit, comprising:

standard cells arranged in rows and columns; and

tap cells arranged in rows and columns, the tap cells each comprising:

a substrate having a first dopant type; and

a well region in the substrate having a second dopant type different from the first dopant type,

wherein

fewer than a total quantity of tap cells included in the integrated circuit comprise a substrate contact,

a different quantity of tap cells comprise a well contact, and

substrate contacts in a same column of tap cells are separated by a distance greater than a maximum distance set by a design rule established by an integrated circuit design system specifying the maximum distance between substrate contacts to prevent latchup.