Inverting buck-boost converter drive circuit and method

1. A circuit, comprising:

a high-side power transistor having a source-drain path coupled between a first node and a second node;

a low-side power transistor having a source-drain path coupled between the second node and a third node;

a high-side drive circuit having an input configured to receive a drive signal and an output configured to drive a control terminal of said high-side power transistor, said high-side drive circuit including a capacitive driver comprising a first bootstrap capacitor having a first capacitor terminal coupled to said input of the high-side drive circuit and a second capacitor terminal coupled to the control terminal of said high-side power transistor; and

a low-side drive circuit having an input configured to receive a complement drive signal and an output configured to drive a control terminal of said low-side power transistor, said low-side drive circuit including a level-shifting driver; and

wherein said capacitive driver comprises:

a first half-bridge driver having an input responsive to said drive signal; and

wherein the first capacitor terminal of the first bootstrap capacitor is coupled to an output of the first half-bridge driver;

an inverting circuit configured to invert the output of the first half-bridge driver;

a second bootstrap capacitor having a first capacitor terminal coupled to an output of the inverting circuit and a second capacitor terminal coupled to a fourth node; and

a transistor having a source-drain path coupled between the control terminal of the high-side power transistor and the second node, said transistor having a control terminal coupled to said fourth node.

2. The circuit of claim 1 , wherein the first node is coupled to receive a positive supply voltage and the third node is configured to output a negative supply voltage, further including a load circuit coupled to the third node.

3. The circuit of claim 1 , wherein said level-shifting driver comprises:

a level shifting circuit having an input responsive to said complement drive signal; and

a second half-bridge driver having an input responsive an output of the level shifting circuit and an output coupled to the control terminal of said low-side power transistor.

4. The circuit of claim 3 , wherein said level-shifting driver further comprises a regulator circuit configured to generate a clamp voltage supplying power to said level shifting circuit and said second half-bridge driver.

5. The circuit of claim 1 , wherein said capacitive driver further comprises:

a switching transistor having a source drain path coupled between the second capacitor terminal of the first bootstrap capacitor and the control terminal of the high-side power transistor, wherein a control terminal of the switching transistor is coupled to said first node.

6. The circuit of claim 5 , wherein said capacitive driver further comprises a diode having a first terminal coupled to said first node and a second terminal coupled to a fifth node positioned between the second capacitor terminal of the first bootstrap capacitor and the switching transistor.

7. The circuit of claim 1 , wherein the capacitive driver further comprises a clamping circuit having a first terminal coupled to the control terminal of said transistor and a second terminal coupled to the second node.

8. The circuit of claim 1 , further comprising a pulse width modulated (PWM) control circuit configured to generate said drive signal and said complement drive signal as PWM signals.

9. The circuit of claim 8 , further comprising a feedback circuit having an input coupled to said third node and an output coupled to an input of said PWM control circuit.

10. The circuit of claim 8 , further comprising a current sensing circuit configured to sense current flow through said high-side power transistor and output a current sense signal to an input of said PWM control circuit.

11. The circuit of claim 8 , further comprising a discontinuous mode detection circuit coupled to said low-side power transistor and configured to generate a discontinuous mode detection signal for application to an input of said PWM control circuit.

12. The circuit of claim 1 , wherein the circuit is implemented as an integrated circuit.

13. A circuit, comprising:

a high-side power transistor having a source-drain path coupled between a first node and a second node;

a low-side power transistor having a source-drain path coupled between the second node and a third node;

a high-side drive circuit having an input configured to receive a drive signal and an output configured to drive a control terminal of said high-side power transistor, said high-side drive circuit including a capacitive driver; and

a low-side drive circuit having an input configured to receive a complement drive signal and an output configured to drive a control terminal of said low-side power transistor, said low-side drive circuit including a level-shifting driver;

wherein said capacitive driver comprises:

a first half-bridge driver having an input responsive to said drive signal;

a first bootstrap capacitor coupled between an output of the first half-bridge driver and the control terminal of the high-side power transistor;

an inverting circuit configured to invert the output of the first half-bridge driver;

a second bootstrap capacitor coupled between an output of the inverting circuit and a fourth node; and

a transistor having a source-drain path coupled between the control terminal of the high-side power transistor and the second node, said transistor having a control terminal coupled to said fourth node.

14. The circuit of claim 13 , wherein the first node is coupled to receive a positive supply voltage and the third node is configured to output a negative supply voltage, further including a load circuit coupled between the third node and the second node.

15. The circuit of claim 13 , wherein said level-shifting driver comprises:

a level shifting circuit having an input responsive to said complement drive signal; and

a second half-bridge driver having an input responsive an output of the level shifting circuit and an output coupled to the control terminal of said low-side power transistor.

16. The circuit of claim 15 , wherein said level-shifting driver further comprises a regulator circuit configured to generate a clamp voltage supplying power to said level shifting circuit and said second half-bridge driver.

17. The circuit of claim 13 , wherein said capacitive driver further comprises:

a switching transistor having a source drain path coupled between the first bootstrap capacitor and the control terminal of the high-side power transistor, wherein a control terminal of the switching transistor is coupled to said first node.

18. The circuit of claim 17 , wherein said capacitive driver further comprises a diode coupled between said first node and a fifth node positioned between the first bootstrap capacitor and the switching transistor.

19. The circuit of claim 13 , wherein the capacitive driver further comprises a clamping circuit coupled between the control terminal of said transistor and the second node.

20. The circuit of claim 13 , further comprising a pulse width modulated (PWM) control circuit configured to generate said drive signal and said complement drive signal as PWM signals.

21. The circuit of claim 20 , further comprising a feedback circuit coupled between said third node and an input of said PWM control circuit.

22. The circuit of claim 20 , further comprising a current sensing circuit configured to sense current flow through said high-side power transistor and output a current sense signal to an input of said PWM control circuit.

23. The circuit of claim 20 , further comprising a discontinuous mode detection circuit coupled to said low-side power transistor and configured to generate a discontinuous mode detection signal for application to an input of said PWM control circuit.

24. The circuit of claim 13 , wherein the circuit is implemented as an integrated circuit.